Floating gate transistor having buried strained silicon germanium channel layer

Abstract

A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.

What is claimed is:  
     
       1. A field effect transistor comprising: 
       a) a silicon substrate,  
       b) a source region and a drain region formed in spaced surface regions of the substrate,  
       c) a channel region between the source region and the drain region, the channel region including a Si x Ge 1−x  alloy layer epitaxially grown on the silicon substrate and a silicon cap layer epitaxially grown on the alloy layer,  
       d) a floating gate over and insulated from the channel region, and  
       e) a control gate over and insulated from the floating gate.  
     
     
       2. The field effect transistor as defined by claim  1  wherein the Si x Ge 1−x  alloy layer is graded. 
     
     
       3. The field effect transistor as defined by claim  2  wherein the Si x Ge 1−x  alloy layer is graded from 1−x=0 to a maximum value in the growth direction. 
     
     
       4. The field effect transistor as defined by claim  3  wherein the Si x Ge 1−x  layer is compressively strained. 
     
     
       5. The field effect transistor as defined by claim  4  wherein the thickness of the Si x Ge 1−x  layer is below a critical value to maintain pseudomorphic strain. 
     
     
       6. The field effect transistor as defined by claim  1  wherein the Si x Ge 1−x  layer is compressively strained. 
     
     
       7. The field effect transistor as defined by claim  6  wherein the thickness of the Si x Ge 1−x  layer is below a critical value to maintain pseudomorphic strain. 
     
     
       8. The field effect transistor as defined by claim  1  wherein the Si x Ge 1−x  alloy layer and the silicon cap layer extend into the source region and the drain region. 
     
     
       9. The field effect transistor as defined by claim  8  wherein the silicon substrate has a monocrystalline lattice structure. 
     
     
       10. The field effect transistor as defined by claim  1  wherein the silicon substrate has a monocrystalline lattice structure. 
     
     
       11. A flash EEPROM device having improved electron injection for programming comprising a monocrystalline silicon body having spaced source and drain regions with a channel therebetween, the channel including a graded SiGe alloy layer epitaxially grown on the silicon body and a cap silicon layer epitaxially grown on the SiGe layer, and a gate structure overlying the channel region including a control gate and floating gate between the control gate and the channel region, the control gate and the floating gate being dielectrically isolated from each other and the semiconductor body. 
     
     
       12. The flash EEPROM device as defined by claim  11  wherein the SiGe alloy layer is compressively strained. 
     
     
       13. The flash EEPROM device as defined by claim  12  wherein the alloy layer is Si x Ge 1−x  and is graded from 1−x=0 to  1−x  being a maximum value. 
     
     
       14. The flash EEPROM device as defined by claim  13  wherein the SiGe layer and the cap layer extend into the source and drain.