Method of fabricating a multi-chip module package

Abstract

A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.

What is claimed is:  
     
       1. A method of a multi-chip module (MCM) package, comprising: 
       providing a substrate, the substrate having an insulating core and a conductive layer, wherein the conductive layer covers a bottom surface of the insulating core;  
       forming a first opening in the substrate to penetrate through the insulating core and the conductive layer;  
       adhering an adhesive tape to cover a surface of the conductive layer, wherein the first opening exposes a portion of a top surface of the adhesive tape;  
       adhering a first chip onto the exposed top surface of the adhesive tape, wherein the first chip has an active surface and a back surface, and a plurality of bonding pads are formed on the active surface of the first chip, the back surface of the first chip is adhered onto the adhesive tape such that the first chip is located firmly on the adhesive tape;  
       forming a patterned dielectric layer to fill into the first opening in order to cover a portion of the exposed top surface of the adhesive tape, the active surface of the first chip, the bonding pads of the chip and the insulating core, a plurality of second openings and third openings formed in the patterned dielectric layer, wherein the second openings expose the bonding pads of the first chip and the third openings penetrate through the patterned dielectric layer, the insulating core and the conductive layer;  
       electroplating a metal layer on sidewalls of the second openings and the third openings, and to cover the patterned dielectric layer;  
       after the electroplating process, removing the adhesive tape to expose the conductive layer, the back surface of the first chip and a portion of the patterned dielectric layer;  
       patterning the metal layer and the conductive layer to form a patterned metal and a patterned conductive layer are formed;  
       forming a patterned solder mask layer to cover surfaces of the patterned metal layer and the patterned conductive layer, wherein a plurality of fourth openings and fifth openings are formed on the patterned solder mask layer to expose respectively a portion of the patterned metal layer and a portion of the patterned conductive layer;  
       performing a solder ball process to form a plurality of solder balls on the fifth openings, wherein a reflow process is carried out to electrically connect the solder balls to the patterned conductive layer; and  
       performing a die adhering process to electrically connect at least a second chip to the patterned metal layer via the fourth openings.  
     
     
       2. The method of  claim 1 , wherein the second chip further comprises a active surface and a plurality of conductive bumps are formed on the active surface of the second chip, a connection process between the second chip to the substrate, comprising: 
       performing a reflow process to electrically connect the conductive bumps to the exposed patterned metal layer via the fourth openings; and  
       filling an underfilling material into gaps between the active surface of the second chip and the patterned solder mask layer.  
     
     
       3. The method of  claim 1 , wherein the second chip further comprises an active surface and a back surface, and a plurality of conductive bumps are formed on the active surface of the second chip, a connection process between the second chip to the substrate, comprising: 
       adhering the back surface of the second chip to the patterned solder mask layer;  
       performing a wire bonding process to electrically connect the bonding pads of the second chip to the exposed patterned metal layer via the fourth openings by utilizing a plurality of conductive wires; and  
       performing molding process to encapsulate the second chip, the conductive wires, the fourth openings, a portion of patterned metal layer and a portion of patterned solder mask layer.  
     
     
       4. The method of  claim 1 , wherein a method of forming the first opening in the substrate includes a punching method. 
     
     
       5. The method of  claim 1 , wherein before patterning the metal layer and the conductive layer, a plug filling process is carried out to fill a plug material into the third openings. 
     
     
       6. The method of  claim 1 , wherein the method further comprises a planarizing process to planarize the surface of the metal layer before patterning the metal layer and the conductive layer. 
     
     
       7. The method of  claim 6 , wherein the planarizing process comprises a chemical mechanical polishing (CMP) process. 
     
     
       8. The method of  claim 1 , wherein the step of patterning the dielectric layer comprises: 
       forming a dielectric layer to fill the first opening and cover the insulating core layer, a portion of the adhesive tape, the active surface of the first chip and the bonding pads of the first chip;  
       forming second openings in the dielectric layer to expose the bonding pads; and  
       forming the third openings in the dielectric layer to penetrate the dielectric layer, the insulating core and the conductive layer.  
     
     
       9. The method of  claim 8 , wherein a method of forming the second openings comprises a laser drilling method. 
     
     
       10. The method of  claim 8 , wherein a method of forming the second openings further comprises: 
       forming a patterned photoresist layer to cover the dielectric layer;  
       using the patterned photoresist layer as a mask to etch the dielectric layer in order to form the second openings such that the bonding pads are exposed.  
     
     
       11. The method of  claim 8 , wherein the method of forming the third openings comprises a machine drilling method. 
     
     
       12. The method of  claim 8 , wherein before forming the second openings, a planarizing process is carried out to planarize a surface of the dielectric layer. 
     
     
       13. The method of  claim 12 , wherein the planarizing process comprises a chemical mechanical polishing (CMP) method. 
     
     
       14. A method of a multi-chip module (MCM) package, comprising: 
       providing a substrate, the substrate having an insulating core and a conductive layer, wherein the conductive layer covers a bottom surface of the insulating core;  
       forming a first opening in the substrate to penetrate through the insulating core and expose a portion of the conductive layer;  
       adhering a first chip onto the exposed conductive layer, wherein the first chip has an active surface and a back surface, and a plurality of bonding pads are formed on the active surface of the first chip, the back surface of the first chip is adhered on the conductive layer such that the first chip is located firmly on the conductive layer;  
       forming a patterned dielectric layer to fill into the first opening in order to cover a portion of the exposed conductive layer, the active surface of the first chip, the bonding pads of the first chip and the insulating core, a plurality of second openings and third openings formed in the patterned dielectric layer, wherein the second openings expose the bonding pads of the first chip and the third openings penetrate through the patterned dielectric layer, the insulating core and the conductive layer;  
       electroplating a metal layer on sidewalls of the second openings and the third openings, and to cover the patterned dielectric layer;  
       patterning the metal layer and the conductive layer to form a patterned metal and a patterned conductive layer are formed;  
       forming a patterned solder mask layer to cover surfaces of the patterned metal layer and the patterned conductive layer, wherein a plurality of fourth openings and fifth openings are formed on the patterned solder mask layer to expose a portion of the patterned metal layer and a portion of the patterned conductive layer respectively;  
       performing a solder ball process to form a plurality of solder balls on the fifth openings, wherein a reflow process is carried out to electrically connect the solder balls to the patterned conductive layer; and  
       performing a die adhering process to electrically connect at least a second chip to the patterned metal layer via the fourth openings.  
     
     
       15. The method of  claim 14 , wherein the second chip has an active surface, and a plurality of conductive bumps are formed on the active surface of the second chip, a connection process of the second chip to the substrate, comprising: 
       performing a reflow process to electrically connect the conductive bumps to the exposed patterned metal layer via the fourth openings; and  
       filling an underfilling material into gaps between the active surface of the second chip and the patterned solder mask layer.  
     
     
       16. The method of  claim 1 , wherein the second chip further comprises an active surface and a back surface, and a plurality of conductive bumps are formed on the active surface of the second chip, a connection process of the second chip to the substrate, comprising: 
       adhering the back surface of the second chip to the patterned solder mask layer such that the second chip is located firmly on the patterned solder mask layer;  
       performing a wire bonding process to electrically connect the bonding pads of the second chip to the exposed patterned metal layer via the fourth openings by utilizing a plurality of conductive wires; and  
       performing a molding process to encapsulate the second chip, the conductive wires, the fourth openings, a portion of patterned metal layer and a portion of patterned solder mask layer.  
     
     
       17. The method of  claim 14 , wherein a method of forming the first opening in the substrate includes a machine drilling method. 
     
     
       18. The method of  claim 14 , wherein before patterning the metal layer and the conductive layer, a plug filling process is carried out to fill the third openings with a plug material. 
     
     
       19. The method of  claim 14 , wherein the method further comprises a planarizing process to planarize the surface of the metal layer before patterning the metal layer and the conductive layer. 
     
     
       20. The method of  claim 19 , wherein the planarizing process comprises a chemical mechanical polishing (CMP) process. 
     
     
       21. The method of  claim 14 , wherein the step of patterning the dielectric layer further comprises: 
       forming a dielectric layer to fill the first opening and cover the insulating core layer, a portion of the conductive layer, the active surface of the first chip and the bonding pads of the first chip;  
       forming second openings in the dielectric layer to expose the bonding pads; and  
       forming the third openings in the dielectric layer to penetrate the dielectric layer, the insulating core and the conductive layer.  
     
     
       22. The method of  claim 21 , wherein a method of forming the second openings comprises a laser drilling method. 
     
     
       23. The method of  claim 21 , wherein a method of forming the second openings further comprises: 
       forming a patterned photoresist layer to cover the dielectric layer;  
       using the patterned photoresist layer as a mask to etch through the dielectric layer such that the second openings are formed to expose the bonding pads.  
     
     
       24. The method of  claim 21 , wherein a method of forming the third openings comprises a machine drilling method. 
     
     
       25. The method of  claim 21 , wherein before forming the second openings, a planarizing process is carried out to planarize a surface of the dielectric layer. 
     
     
       26. The method of  claim 25 , wherein the planarizing process comprises a chemical mechanical polishing (CMP) method.