Lead frame decoupling capacitor semiconductor device packages including the same and methods

Abstract

A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (V cc ), while the other is connectable to a power supply ground (V ss ). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor. Lead fingers which are connected to the power supply source (V cc ) are preferably grouped into at least one group and flank the remainder of the lead fingers so that they are not interleaved therewith. Preferably, upon attachment of the lead frame assembly to a semiconductor device, the decoupling capacitor extends over a substantial portion of the latter.

What is claimed is:  
     
       1. A semiconductor die assembly, comprising: 
       a semiconductor device including a plurality of bond pads on an active surface thereof; and  
       a decoupling capacitor structure including:  
       a first electrode comprising at least a portion of a first electrically conductive bus of a first lead frame layer, said first bus disposed in immediate, electrically isolated proximity to said active surface, said first lead frame layer including a first lead finger group comprising a first plurality of lead fingers located substantially centrally along an edge of the assembly, at least some of said bond pads being electrically connected to lead fingers of said first group, said at least some of said bond pads being electrically connected to said first electrically conductive bus; and  
       a second electrode comprising at least a portion of a second electrically conductive bus of a second lead frame layer, said second electrically conductive bus superimposed with respect to at least a portion of said first electrically conductive bus in immediate, electrically isolated proximity thereto, said second lead frame layer including a second lead finger group comprising a second plurality of lead fingers laterally adjacent said first lead finger group, at least one of said bond pads in communication with said second electrically conductive bus.  
     
     
       2. The assembly of  claim 1 , wherein the lead fingers of said first lead finger group are mutually adjacent. 
     
     
       3. The assembly of  claim 2 , wherein said at least two second lead finger groups laterally flank said second lead finger group. 
     
     
       4. The assembly of  claim 1 , wherein one of said first and second electrically conductive buses is connectable to a power supply ground (V ss ). 
     
     
       5. The assembly of  claim 1 , wherein one of said first and second electrically conductive buses is connectable to a power supply source (V cc ). 
     
     
       6. The assembly of  claim 1 , wherein said first and second lead frame layers form a lead frame. 
     
     
       7. The assembly of  claim 6 , wherein said lead frame comprises a leads-over-chip lead frame and said first and second lead finger groups are affixed directly to said active surface. 
     
     
       8. The assembly of  claim 6 , wherein said lead frame comprises a die-attach paddle to which said semiconductor r device is attached. 
     
     
       9. The assembly of  claim 8 , wherein said lead fingers of said first and second lead finger groups terminate proximate a peripheral edge of said semiconductor device. 
     
     
       10. The assembly of  claim 1 , wherein said first electrically conductive bus is electrically connected to at least one lead finger of said first lead finger group. 
     
     
       11. The assembly of  claim 1 , wherein said second electrically conductive bus is electrically connected to at least one lead finger of said second lead finger group. 
     
     
       12. The assembly of  claim 1 , wherein said first electrically conductive bus extends over a surface of said semiconductor device. 
     
     
       13. The assembly of  claim 1 , wherein said second electrically conductive bus extends over a surface of said semiconductor device. 
     
     
       14. The assembly of  claim 1 , further comprising an insulator element disposed between said first electrically conductive bus and said second electrically conductive bus. 
     
     
       15. The assembly of  claim 14 , wherein said insulator element comprises a nonconductive adhesive. 
     
     
       16. The assembly of  claim 14 , wherein said insulator element comprises an insulating film having an adhesive on opposing surfaces thereof, one surface being adhered to at least one of said first lead frame layer or said second lead frame layer and another surface to at least one voltage reference plane. 
     
     
       17. The assembly of  claim 14 , wherein said first electrically conductive bus, said second electrically conductive bus, and said insulator element form a decoupling capacitor. 
     
     
       18. The assembly of  claim 1 , wherein an outermost of said first and second electrically conductive buses includes projections extending away from said semiconductor device in a direction nonparallel to planes in which said first and second electrically conductive buses are located. 
     
     
       19. The assembly of  claim 18 , further comprising a packaging material extending over said first electrically conductive bus and said second electrically conductive bus. 
     
     
       20. The assembly of  claim 19 , wherein said projections extend through said packaging material to an exterior surface thereof. 
     
     
       21. The assembly of  claim 1 , further comprising a packaging material through which only outer ends of said lead fingers extend. 
     
     
       22. A lead frame assembly, comprising: 
       a first conductive bus in a first layer;  
       a second conductive bus in a second layer, said second conductive bus being superimposed over said first conductive bus in electrical isolation therefrom so as to form a decoupling capacitor;  
       a first group of lead fingers extending from said first conductive bus substantially toward a single peripheral edge of the assembly, said first group of lead fingers being located substantially centrally along an edge of the assembly; and  
       a second group of lead fingers extending from said second conductive bus substantially toward said single peripheral edge, said second group of lead fingers being located laterally adjacent said first group of lead fingers, said decoupling capacitor in communication with at least one lead finger of each of said first and second groups.  
     
     
       23. The assembly of  claim 22 , wherein at least one lead finger of said first group is electrically connected to said first bus. 
     
     
       24. The assembly of  claim 22 , wherein at least one lead finger of said second group is electrically connected to said second bus. 
     
     
       25. The assembly of  claim 22 , wherein one of said first and second buses is connectable to a power supply ground (V ss ). 
     
     
       26. The assembly of  claim 22 , wherein one of said first and second buses is connectable to a power supply source (V cc ). 
     
     
       27. The assembly of  claim 22 , wherein all of the lead fingers of said first group are mutually adjacent. 
     
     
       28. The assembly of  claim 27 , wherein the lead fingers of said at least two second lead finger groups flank said first lead finger group. 
     
     
       29. The assembly of  claim 22 , wherein at least one of said first and second buses includes projections extending away from a plane of the other of said second and first buses. 
     
     
       30. The assembly of  claim 22 , wherein at least one of said first and second buses comprises a die-attach paddle. 
     
     
       31. A semiconductor die assembly, comprising: 
       a semiconductor device including a plurality of bond pads on an active surface thereof; and  
       a decoupling capacitor adjacent said surface, said decoupling capacitor comprising:  
       a first electrode comprising at least a portion of a first electrically conductive bus of a first lead frame layer disposed in immediate, electrically isolated proximity to said active surface, said first lead frame layer including a first lead finger group comprising a first plurality of mutually adjacent lead fingers located substantially centrally along an edge of the assembly, at least some of said bond pads being electrically connected to lead fingers of said first group, said at least some of said bond pads being electrically connected to said first electrically conductive bus; and  
       a second electrode comprising at least a portion of a second electrically conductive bus of a second lead frame layer, said second electrically conductive bus superimposed with respect to at least a portion of said first electrically conductive bus in immediate, electrically isolated proximity thereto, said second lead frame layer including a second lead finger group comprising a second plurality of lead fingers laterally adjacent said first lead finger group, at least one of said bond pads in communication with said second electrically conductive bus.  
     
     
       32. The assembly of  claim 31 , wherein said second electrically conductive bus is electrically connectable to a power supply source (V cc ). 
     
     
       33. The assembly of  claim 31 , wherein said first electrically conductive bus is electrically connectable to a power supply ground (V ss ). 
     
     
       34. The assembly of  claim 31 , further comprising an insulator element disposed between said first electrically conductive bus and said second electrically conductive bus. 
     
     
       35. A semiconductor die assembly, comprising: 
       a semiconductor device including a plurality of bond pads on an active surface thereof;  
       a first lead frame layer disposed in immediate, electrically isolated proximity to said active surface and including a first electrically conductive bus and a first lead finger group comprising a first plurality of lead fingers located substantially centrally along an edge of the assembly, selected lead fingers being electrically connectable to a power supply ground (V ss ), at least some of said bond pads being electrically connected to the plurality of lead fingers of said first group, said at least some of said bond pads being electrically connected to said first electrically conductive bus; and  
       a second lead frame layer including a second electrically conductive bus superimposed with respect to at least a portion of said first electrically conductive bus in immediate, electrically isolated proximity thereto, at least portions of said first and second electrically conductive buses forming a decoupling capacitor, said second lead frame layer including a second lead finger group comprising a second plurality of lead fingers laterally adjacent said first lead finger group, selected lead fingers being electrically connectable to a power supply source (V cc ), at least one of said bond pads in communication with said second electrically conductive bus.  
     
     
       36. A semiconductor device assembly, comprising: 
       a substantially planar substrate including an outer periphery;  
       a semiconductor device disposed at least partially upon said substantially planar substrate and including a plurality of bond pads on an active surface thereof;  
       a first lead frame layer positioned at least partially over said substantially planar substrate and in immediate, electrically isolated proximity to said active surface of said semiconductor device, said first lead frame layer including a first bus and a first lead finger group located substantially centrally along an edge of the assembly; and  
       a second lead frame layer positioned at least partially over said substantially planar substrate and including:  
       a second lead finger group laterally adjacent said first lead finger group; and  
       a second bus superimposed with respect to at least a portion of said first bus in immediate, electrically isolated proximity thereto so as to form respective first and second electrodes of a decoupling capacitor.  
     
     
       37. The semiconductor device assembly of  claim 36 , wherein selected lead fingers of said first and second groups extend over said outer periphery. 
     
     
       38. The semiconductor device assembly of  claim 36 , wherein each lead finger of said first and second lead finger groups extend across a single side of said outer periphery. 
     
     
       39. The semiconductor device assembly of  claim 36 , wherein the lead fingers of said first lead finger group are mutually adjacent. 
     
     
       40. The semiconductor device assembly of  claim 38 , wherein said at least two second lead finger groups flank said first lead finger group. 
     
     
       41. The semiconductor device assembly of  claim 36 , wherein at least one of said plurality of bond pads is electrically connected to said power supply ground (V ss ). 
     
     
       42. The semiconductor device assembly of  claim 36 , wherein at least one of said plurality of bond pads is electrically connected to said power supply source (V cc ). 
     
     
       43. The semiconductor device assembly of  claim 36 , wherein said first and second lead frame layers form a lead frame. 
     
     
       44. The semiconductor device assembly of  claim 43 , wherein said lead frame overlies said active surface. 
     
     
       45. The semiconductor device assembly of  claim 36 , wherein said first bus is electrically connected to at least one lead finger of said first group. 
     
     
       46. The semiconductor device assembly of  claim 36 , wherein said second bus is electrically connected to at least one lead finger of said second group. 
     
     
       47. The semiconductor device assembly of  claim 36 , wherein at least one of said first and second buses includes projections extending away from a plane of said semiconductor device. 
     
     
       48. The semiconductor device assembly of  claim 47 , further comprising a packaging material extending over said first and second buses. 
     
     
       49. The semiconductor device assembly of  claim 48 , wherein said projections extend through said packaging material to an exterior surface thereof. 
     
     
       50. The assembly of  claim 36 , further comprising a packaging material through which outer ends of lead fingers of said lead finger groups extend. 
     
     
       51. The assembly of  claim 1 , comprising at least two second lead finger groups. 
     
     
       52. The assembly of  claim 22 , comprising at least two second lead finger groups. 
     
     
       53. The assembly of  claim 36 , comprising at least two second lead finger groups.