Method for forming integrated circuit having MONOS device and mixed-signal circuit

Abstract

A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

What is claim is:  
     
       1. A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising: 
       providing a substrate having an array region having a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence and a periphery region having said first dielectric layer thereon;  
       forming a first conductive layer over said array region and said periphery region;  
       forming a photoresist layer over said array region;  
       implanting dopant ions into said first conductive layer;  
       removing said photoresist layer;  
       patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;  
       removing said third dielectric layer to expose said second dielectric layer;  
       removing said exposed first dielectric layer on said periphery region to expose said substrate;  
       oxidizing said second dielectric layer, said substrate, said second conductive layer and said third conductive layer to form a fourth dielectric layer therein;  
       forming a fourth conductive layer over said fourth dielectric layer; and  
       patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said fourth dielectric layer and said third conductive layer.  
     
     
       2. The method according to  claim 1 , wherein said first dielectric layer, said second dielectric layer and said third dielectric layer comprise a silicon dioxide-silicon nitride-silicon dioxide layer. 
     
     
       3. The method according to  claim 1 , wherein said first conductive layer comprises a polysilicon layer. 
     
     
       4. The method according to  claim 1 , wherein said dopant ions comprise n-type dopant ions. 
     
     
       5. The method according to  claim 1 , wherein said dopant ions comprise p-type dopant ions. 
     
     
       6. The method according to  claim 1 , wherein the oxidation process of said second dielectric layer, said substrate, said second conductive layer and said third conductive layer comprises an in situ steam generated oxidation process. 
     
     
       7. The method according to  claim 1 , wherein said fourth dielectric layer comprises a silicon dioxide layer. 
     
     
       8. The method according to  claim 1 , wherein said fourth conductive layer comprises a polysilicon layer. 
     
     
       9. A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising: 
       providing a substrate having an array region having a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer stacked in sequence and a periphery region having said first silicon dioxide layer thereon;  
       forming a first conductive layer over said array region and said periphery region;  
       forming a photoresist layer over said array region;  
       implanting dopant ions into said first conductive layer;  
       removing said photoresist layer;  
       patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;  
       removing said second silicon dioxide layer to expose said silicon nitride layer;  
       removing said exposed first silicon dioxide layer on said periphery region to expose said substrate;  
       oxidizing said silicon nitride layer, said substrate, said second conductive layer and said third conductive layer to form a third silicon dioxide layer therein;  
       forming a fourth conductive layer over said third silicon dioxide layer; and  
       patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said third silicon dioxide layer and said third conductive layer.  
     
     
       10. The method according to  claim 9 , wherein said first conductive layer comprises a polysilicon layer. 
     
     
       11. The method according to  claim 9 , wherein said dopant ions comprise n-type dopant ions. 
     
     
       12. The method according to  claim 9 , wherein said dopant ions comprise p-type dopant ions. 
     
     
       13. The method according to  claim 9 , wherein the oxidation process of said silicon nitride layer, said substrate, said second conductive layer and said third conductive layer comprises an in situ steam generated oxidation process. 
     
     
       14. The method according to  claim 9 , wherein said fourth conductive layer comprises a polysilicon layer and WSi x . 
     
     
       15. A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising: 
       providing a substrate having an array region having a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer stacked in sequence and a periphery region having said first silicon dioxide layer thereon;  
       forming a first conductive layer over said array region and said periphery region;  
       forming a photoresist layer over said array region;  
       implanting dopant ions into said first conductive layer;  
       removing said photoresist layer;  
       patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;  
       removing said second silicon dioxide layer to expose said silicon nitride layer;  
       removing said exposed first silicon dioxide layer on said periphery region to expose said substrate;  
       oxidizing said silicon nitride layer, said substrate, said second conductive layer and said third conductive layer to form a third silicon dioxide layer therein by an in situ steam generated oxidation process;  
       forming a fourth conductive layer over said third silicon dioxide layer; and  
       patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said third silicon dioxide layer and said third conductive layer.  
     
     
       16. The method according to  claim 15 , wherein said first conductive layer comprises a polysilicon layer. 
     
     
       17. The method according to  claim 15 , wherein said dopant ions comprise n-type dopant ions. 
     
     
       18. The method according to  claim 15 , wherein said dopant ions comprise p-type dopant ions. 
     
     
       19. The method according to  claim 15 , wherein said fourth conductive layer comprises a polysilicon layer and WSi x . 
     
     
       20. The method according to  claim 15 , wherein said fourth conductive layer is formed by a low pressure chemical vapor deposition process.