US6599603B1ExpiredUtility

Silicon wafer

64
Assignee: SHINETSU HANDOTAI KKPriority: Mar 4, 1999Filed: Feb 25, 2000Granted: Jul 29, 2003
Est. expiryMar 4, 2019(expired)· nominal 20-yr term from priority
H10P 36/20C30B 29/06Y10T428/21C30B 15/00
64
PatentIndex Score
9
Cited by
12
References
12
Claims

Abstract

The present invention provides a CZ silicon wafer, wherein the wafer includes rod-like void defects and/or plate-like void defects inside thereof, and a CZ silicon wafer, wherein the silicon wafer includes void defects inside the wafer, a maximum value of a ratio between long side length L 1 and short side length L 2 (L 1 /L 2 ) in an optional rectangle circumscribed the void defect image projected on an optional {110} plane is 2.5 or more, and the silicon wafer including rod-like void defects and/or plate-like void defects inside the wafer, wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm after the heat treatment is ½ or less than that of inside the wafer. According to this, the silicon wafer, which is suitable for expanding reducing effect of void defects by heat treatment up to a deeper region, can be obtained.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A silicon wafer produced by processing a silicon single crystal ingot grown by a Czochralski method, wherein the silicon wafer includes rod-like void defects and/or plate-like void defects inside the wafer and wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm is ½ or less than that of the wafer inside. 
     
     
       2. A silicon wafer produced by processing a silicon single crystal ingot grown by a Czochralski method, wherein the silicon wafer includes void defects inside the wafer, wherein a maximum value of a ratio between long side length L 1  and short side length L 2  (L 1 /L 2 ) of a rectangle projected to circumscribe the void defects in any {110} plane is 2.5 or more and wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 μm is ½ or less than that of the wafer inside. 
     
     
       3. The silicon wafer according to  claim 1 , wherein the silicon single crystal ingot grown by a Czochralski method is doped with nitrogen. 
     
     
       4. The silicon wafer according to  claim 2 , wherein the silicon single crystal ingot grown by a Czochralski method is doped with nitrogen. 
     
     
       5. The silicon wafer according to  claim 1 , wherein the silicon wafer is subjected to heat treatment at a temperature of 1000° C. or more for 10 seconds or more. 
     
     
       6. The silicon wafer according to  claim 2 , wherein the silicon wafer is subjected to heat treatment at a temperature of 1000° C. or more for 10 seconds or more. 
     
     
       7. The silicon wafer according to  claim 3 , wherein the silicon wafer is subjected to heat treatment at a temperature of 1000° C. or more for 10 seconds or more. 
     
     
       8. The silicon wafer according to  claim 4 , wherein the silicon wafer is subjected to heat treatment at a temperature of 1000° C. or more for 10 seconds or more. 
     
     
       9. The silicon wafer according to  claim 5 , wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 um after the heat treatment is ½ or less than that of the silicon wafer before the heat treatment. 
     
     
       10. The silicon wafer according to  claim 6 , wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 um after the heat treatment is ½ or less than that of the silicon wafer before the heat treatment. 
     
     
       11. The silicon wafer according to  claim 7 , wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 um after the heat treatment is ½ or less than that of the silicon wafer before the heat treatment. 
     
     
       12. The silicon wafer according to  claim 8 , wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 um after the heat treatment is ½ or less than that of the silicon wafer before the heat treatment.

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