Electrically programmable memory cell configuration and method for fabricating it

Abstract

A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric disposed on sidewalls of the depression. Since the floating gate electrode has a larger area than the channel region, a capacitance formed by a control gate electrode applied on the floating gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region. Two source/drain regions of the transistor likewise adjoin the sidewalls of the depression. An insulation, which is thicker than the first dielectric, isolates the floating gate electrode from the source/drain regions, so that the source/drain regions do not contribute to the coupling ratio.

We claim:  
     
       1. An electrically programmable memory cell configuration, comprising: 
       a substrate having a surface and depressions each with a bottom and mutually opposite sidewalls formed therein;  
       a plurality of memory cells having planar transistors, each of said memory cells having a planar transistor disposed in said substrate, said planar transistor having:  
       two source/drain regions adjoining two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression;  
       a channel region disposed in said substrate in at least part of said bottom of said depression;  
       a first dielectric layer disposed on said bottom of said depression in a region of said channel region, said dielectric layer having a thickness allowing tunneling of electrons during programming, said channel region having a cross section being parallel to said surface of said substrate and intersects said two source/drain regions;  
       a floating gate electrode adjoining said first dielectric and partially disposed on at least two of said mutually opposite sidewalls of said depression and said depression being constricted but not filled by said floating gate electrode;  
       a second dielectric layer;  
       a control gate electrode disposed above said floating gate electrode and insulated from said floating gate electrode by said second dielectric; and  
       an insulation spacer disposed on two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression for preventing a capacitance between said two source/drain regions and said floating gate electrode, said insulation spacer having a thickness eliminating tunneling during programming, said first dielectric layer extending from said insulation spacer of at least one of said sidewalls to the other of said sidewalls on said bottom of said depression, and parts of said floating gate electrode disposed on said two of said sidewalls of said depression adjoining said insulation spacer.  
     
     
       2. The memory cell configuration according to  claim 1 , including: 
       a word line electrically connected to said control gate electrode; and  
       connecting lines running between said two source/drain regions, none of said connecting lines between said two source/drain regions runs parallel to a course of said word line.  
     
     
       3. The memory cell configuration according to  claim 1 , including insulating structures disposed in said substrate, said depression disposed between two of said insulating structures and said depression having two further sidewalls defined by said insulating structures, and said floating gate electrode likewise adjoins said two further sidewalls. 
     
     
       4. The memory cell configuration according to  claim 1 , wherein said floating gate electrode does not project out from said depression. 
     
     
       5. The memory cell configuration according to  claim 1 , wherein each of said two source/drain regions is formed of a first part adjoining one of said two sidewalls of said depression and said channel region, and a second part being doped more heavily than said first part and adjoins said first part. 
     
     
       6. The memory cell configuration according to  claim 2 , wherein said transistors which are adjacent to one another transversely with respect to said word line are connected in series and form a bit line, two of said transistors which are adjacent to one another transversely with respect to said word line in each case have a common source/drain region. 
     
     
       7. The memory cell configuration according to  claim 2 , including a bit line, said transistors which are adjacent to one another transversely with respect to said word line are connected in parallel with one another, and one of said source/drain regions in each case is connected to said bit line, and two of said transistors which are adjacent to one another transversely with respect to said word line in each case have a common source/drain region. 
     
     
       8. The memory cell configuration according to  claim 1 , wherein the memory cell configuration has a periphery containing further transistors disposed in said substrate, said further transistors selected from the group consisting of said planar transistors and planar high-voltage transistors. 
     
     
       9. A method for fabricating an electrically programmable memory cell configuration, which comprises the steps of: 
       providing a substrate;  
       producing a depression having a bottom and sidewalls in the substrate;  
       applying a first dielectric disposed at least partially at the bottom of the depression, the first dielectric dimensioned with a thickness allowing tunneling during programming;  
       producing a channel region of a planar transistor of a memory cell in the substrate, the channel region adjoining the first dielectric;  
       forming two source/drain regions of the planar transistor by implantation of a surface of the substrate such that the two source/drain regions adjoin two mutually opposite sidewalls of the depression and extend from the surface of the substrate to the bottom of the depression and that a cross section through the channel region being parallel to the surface of the substrate, intersects the two source/drain regions;  
       providing an insulation spacer extending along the sidewalls of the depression from the surface of the substrate to the bottom of the depression to the two mutually opposite sidewalls of the depression;  
       providing the first dielectric layer extending from the insulation spacer of at least one of the sidewalls to the other of the sidewalls on the bottom of the depression;  
       applying a conductive layer to the depression resulting in the depression being constricted, but not filled, by the conductive layer;  
       patterning the conductive layer thus forming a floating gate electrode of the planar transistor, the floating gate electrode adjoining the first dielectric and the insulation spacer, the insulation spacer preventing a formation of a capacitance between the floating gate electrode and the two source/drain regions, and the insulation spacer dimensioned with a thickness eliminating tunneling during programming;  
       forming a second dielectric above the floating gate electrode; and  
       forming a control gate electrode above the second dielectric.  
     
     
       10. The method according to  claim 9 , which comprises: 
       producing a connecting line between the two source/drain regions; and  
       producing a word line such that it is electrically connected to the control gate electrode and that the connecting line between the two source/drain regions is not parallel to a course of the word line.  
     
     
       11. The method according to  claim 9 , which comprise: 
       producing first insulating structures in the substrate;  
       forming the depression between two of the first insulating structures, the first insulating structures forming two of the sidewalls of the depression; and  
       patterning the floating gate electrode such that it also adjoins the first insulating structures and thus at least four of the sidewalls of the depression.  
     
     
       12. The method according to  claim 9 , which comprises: 
       after the conductive layer has been applied, depositing a planarization material and planarizing the planarization material until parts of the conductive layer situated outside the depression are uncovered; and  
       planarizing parts of the conductive layer situated outside of the depression until the parts are removed, the floating gate electrode which does not project out from the depression thereby being produced.  
     
     
       13. The method according to  claim 10 , which comprises: 
       producing a first part of each of the two source/drain regions, the first part adjoins one of the two mutually opposite sidewalls of the depression and the channel region;  
       after the word line has been produced, depositing and etching back a material for producing spacers along sidewalls of the word line; and  
       producing a second part of each of the two source/drain regions by implantation with an aid of the spacers being used as a mask, the second part being doped more heavily than the first part and adjoins the first part.  
     
     
       14. The method according to  claim 10 , which comprises: 
       forming the planar transistor as one of a plurality of planar transistors produced in a plurality of depressions, each two of the planar transistors which are adjacent to one another transversely with respect to the word line share a common source/drain region; and  
       forming a bit line by series-connecting the planar transistors which are adjacent to one another transversely with respect to the word line.  
     
     
       15. The method according to  claim 10 , which comprises: 
       forming the planar transistor as one of a plurality of transistors produced in a plurality of depressions, each two of the planar transistors which are adjacent to one another transversely with respect to the word line share a common source/drain region; and  
       producing a bit line connected to a respective source/drain regions of each of the planar transistors which are adjacent to one another transversely with respect to the word line.  
     
     
       16. The method according to  claim 11 , which comprises: 
       producing at least one second insulating structure of a further planar transistor of a periphery of the memory cell configuration and a third insulating structure of a planar high-voltage transistor of the periphery in the substrate together with the first insulating structures;  
       before the control gate electrode is produced, producing a gate dielectric of the further planar transistor of the periphery and a gate dielectric of the planar high-voltage transistor of the periphery;  
       applying and patterning a further layer thereby producing the control gate electrode which is part of a word line, a gate electrode of the further planar transistor of the periphery and a gate electrode of the planar high-voltage transistor of the periphery;  
       forming first parts of the two source/drain regions of the planar transistor of the memory cell, first parts of source/drain regions of the further planar transistor of the periphery, and first parts of source/drain regions of the planar high-voltage transistor of the periphery by implantation, the word line, the gate electrode of the further planar transistor of the periphery and the gate electrode of the planar high-voltage transistor of the periphery acting as masks;  
       depositing and etching back a material for producing spacers along sidewalls of the word line;  
       forming further spacers on sidewalls of the gate electrode of the further planar transistor of the periphery; and  
       producing second parts of the two source/drain regions of the planar transistor of the memory cell, second parts of the source/drain regions of the further planar transistor of the periphery and second parts of the source/drain regions of the planar high-voltage transistor of the periphery, where at least the spacers and the further spacers act as a mask.  
     
     
       17. The memory cell configuration according to  claim 5 , including: 
       a word line disposed within said depression and having a portion extending above said surface of said substrate;  
       a spacer adjoining said portion of said word line and covering a portion of said substrate; and  
       said first part of said source/drain regions extending below said portion of said surface of said substrate and said second part of said source/drain regions adjoining said portion of said surface of said substrate.