Etching back process to improve topographic planarization of a polysilicon layer

Abstract

An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole. Then, a bottom antireflective coating (BARC) layer is formed to fill the sunken portion and cover the entire surface of the polysilicon layer. Next, in a first etching step, the BARC layer outside the sunken portion of the polysilicon layer is removed and the BARC layer in the sunken portion of the polysilicon layer is retained to flatten the bottom of the sunken portion. Thereafter, in a second etching step, the etching rate of the polysilicon is decreased and the etching rate of the BARC layer is increased to remove a part of the polysilicon layer outside the sunken portion and retain some of the BARC layer inside the sunken portion, in which the BARC layer remaining in the sunken portion protrudes from the polysilicon layer. Next, the polysilicon layer outside the contact hole is completely removed.

What is claimed is:  
     
       1. An etching back process to improve topographic planarization of a polysilicon layer, comprising steps of: 
       providing a semiconductor substrate having two adjacent insulating structures and a contact hole formed between the two insulating structures;  
       forming a polysilicon layer to fill the contact hole and cover the entire surface of the semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole;  
       forming a bottom antireflective coating (BARC) layer to fill the sunken portion and cover the entire surface of the polysilicon layer;  
       performing a first etching step to completely remove the BARC layer outside the sunken portion of the polysilicon layer and retain the BARC layer in the sunken portion of the polysilicon layer to flatten the bottom of the sunken portion;  
       performing a second etching step to decrease the etching rate of the polysilicon and increase the etching rate of the BARC layer to remove a part of the polysilicon layer outside the sunken portion and retain some of the BARC layer inside the sunken portion, in which the BARC layer remaining in the sunken portion protrudes from the polysilicon layer; and  
       etching the polysilicon layer to completely remove the polysilicon layer outside the contact hole.  
     
     
       2. The etching back process to improve topographic planarization of a polysilicon layer according to  claim 1 , wherein the first etching step uses CF 4  of 40˜60 sccm flow rate as the etching gas. 
     
     
       3. The etching back process to improve topographic planarization of a polysilicon layer according to  claim 1 , wherein the second etching step uses CF 4  of 40˜60 sccm flow rate as the etching gas. 
     
     
       4. The etching back process to improve topographic planarization of a polysilicon layer according to  claim 1 , wherein in the second etching step, the etching selectivity of the polysilicon layer to the BARC layer is 0.75˜0.65. 
     
     
       5. The etching back process to improve topographic planarization of a polysilicon layer according to  claim 1 , further comprising a step of overetching the polysilicon layer to remove the polysilicon layer inside the contact hole to a predetermined depth. 
     
     
       6. The etching back process to improve topographic planarization of a polysilicon layer according to  claim 1 , wherein the polysilicon layer remaining in the contact hole serves as a common source line of a flash memory device.