P
US6794701B2ExpiredUtilityPatentIndex 52

Non-volatile memory

Assignee: MACRONIX INT CO LTDPriority: Mar 20, 2002Filed: Jul 8, 2003Granted: Sep 21, 2004
Est. expiryMar 20, 2022(expired)· nominal 20-yr term from priority
Inventors:KUO TUNG-CHENGLIU CHIEN-HUNGPAN SHYI-SHUHHUANG SHOU-WEI
H10W 20/067H10W 20/021H10D 64/037H10D 30/0413H10B 69/00H10B 43/30
52
PatentIndex Score
1
Cited by
5
References
7
Claims

Abstract

A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A non-volatile memory, comprising: 
       a substrate;  
       a word-line on the substrate;  
       a charge trapping layer between the substrate and the word-line;  
       a contact disposed over the substrate electrically connecting with the word-lind; and  
       a protective metal line electrically connecting with the contact and with a grounding doped region in the substrate, wherein the protective metal line has a first resistance higher than a second resistance of the word-line.  
     
     
       2. The non-volatile memory of  claim 1 , wherein the protective metal line has a first width smaller than a second width of the word-line. 
     
     
       3. The non-volatile memory of  claim 1 , wherein the protective metal line has a first thickness smaller than a second thickness of the word-line. 
     
     
       4. The non-volatile memory of  claim 1 , wherein the protective metal line is electrically connected with the grounding doped region via another contact. 
     
     
       5. The non-volatile memory of  claim 1 , wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. 
     
     
       6. The non-volatile memory of  claim 1 , wherein the word-line comprises: 
       a polysilicon line on the charge trapping layer; and  
       a metal silicide line on the polysilicon line.  
     
     
       7. The non-volatile memory of  claim 6 , wherein the metal silicide line comprises tungsten silicide (Wsi x ).

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