Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same

Abstract

The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

1. A memory cell, comprising:
 a plurality of transistors formed above a semiconducting substrate, each of said transistors comprised of a plurality of doped regions formed in said substrate; and  
 a plurality of local interconnects, each of which are conductively coupled to a doped region of one of said transistors and positioned in an opening in a layer of boron phosphosilicate glass (BPSG) and a dielectric layer positioned above said BPSG layer, said dielectric layer being comprised of a material having a dielectric constant greater than approximately 6.0.  
 
   
   
     2. The memory cell of  claim 1 , said semiconducting substrate is comprised of silicon. 
   
   
     3. The memory cell of  claim 1 , wherein said doped regions are source/drain regions. 
   
   
     4. The memory cell of  claim 1 , wherein said BPSG layer has a thickness of approximately 150-200 nm. 
   
   
     5. The memory cell of  claim 1 , wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide. 
   
   
     6. The memory cell of  claim 1 , wherein said local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon. 
   
   
     7. The memory cell of  claim 1 , wherein said dielectric layer has a thickness that ranges from approximately 300-850 nm. 
   
   
     8. The memory cell of  claim 1 , wherein said dielectric layer is positioned on said BPSG layer. 
   
   
     9. A memory cell, comprising:
 a plurality of transistors formed above a semiconducting substrate comprised of silicon, each of said transistors comprised of a plurality of doped regions formed in said substrate; and  
 a plurality of local interconnects, each of which are conductively coupled to a doped region of one of said transistors and positioned in an opening in a layer of boron phosphosilicate glass (BPSG) and a dielectric layer positioned on said BPSG layer, said dielectric layer being comprised of a material having a dielectric constant greater than approximately 6.0.  
 
   
   
     10. The memory cell of  claim 9 , wherein said doped regions are source/drain regions. 
   
   
     11. The memory cell of  claim 9 , wherein said BPSG layer has a thickness of approximately 150-200 nm. 
   
   
     12. The memory cell of  claim 9 , wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide. 
   
   
     13. The memory cell of  claim 9 , wherein said local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon. 
   
   
     14. The memory cell of  claim 9 , wherein said dielectric layer has a thickness that ranges from approximately 300-850 nm. 
   
   
     15. A memory cell, comprising:
 a plurality of transistors formed above a semiconducting substrate comprised of silicon, each of said transistors comprised of a plurality of doped regions formed in said substrate; and  
 a plurality of local interconnects comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon, each of which are conductively coupled to a doped region of one of said transistors and positioned in an opening in a layer of boron phosphosilicate glass (BPSG) and a dielectric layer positioned on said BPSG layer, said dielectric layer being comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.  
 
   
   
     16. The memory cell of  claim 15 , wherein said doped regions are source/drain regions. 
   
   
     17. The memory cell of  claim 15 , wherein said BPSG layer has a thickness of approximately 150-200 nm. 
   
   
     18. The memory cell of  claim 15 , wherein said dielectric layer has a thickness that ranges from approximately 300-850 nm.