Metal-oxide-semiconductor device including a buried lightly-doped drain region

Abstract

An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

1. A metal-oxide-semiconductor (MOS) device, comprising:
 a semiconductor layer of a first conductivity type;  
 a source region of a second conductivity type formed in the semiconductor layer;  
 a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region;  
 a gate formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions;  
 a buried lightly-doped drain (LDD) region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being formed below at least a portion of the drain region and extending laterally from the drain region to below at least a portion of the gate; and  
 a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer, the second LDD region being self-aligned with a first alignment structure formed substantially concurrently with the gate in a same processing step, the second LDD region being spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.  
 
   
   
     2. The device of  claim 1 , further comprising a shielding structure formed proximate the upper surface of the semiconductor layer and at least partially between the gate and the drain region, the shielding structure being electrically connected to the source region, the shielding structure being spaced laterally from the gate and being substantially non-overlapping relative to the gate. 
   
   
     3. The device of  claim 2 , wherein the shielding structure is formed substantially concurrently with the gate. 
   
   
     4. The device of  claim 2 , wherein a first insulating layer under the gate and a second insulating layer under the shielding structure are formed of different thicknesses in comparison to one another. 
   
   
     5. The device of  claim 1 , wherein the device comprises a diffused MOS (DMOS) device. 
   
   
     6. The device of  claim 5 , wherein the device comprises a lateral DMOS (LDMOS) device. 
   
   
     7. The device of  claim 5 , wherein the device comprises a vertical DMOS device. 
   
   
     8. The device of  claim 1 , wherein the buried LDD region is formed in the semiconductor layer at a depth in a range from about 0.5 micron to about two microns, and the second LDD region is formed in the semiconductor layer at a depth in a range from about 0.05 micron to about 0.5 micron. 
   
   
     9. The device of  claim 1 , further comprising a second alignment structure formed proximate the upper surface of the semiconductor layer and at least partially between the second LDD region and the drain region, wherein the drain region is self-aligned to a first edge of the second alignment structure and the second LDD region is self-aligned with a second edge of the second alignment structure such that the second LDD region is self-aligned with the drain region. 
   
   
     10. The device of  claim 1 , wherein the first alignment structure is removed after forming the second LDD region. 
   
   
     11. An integrated circuit including at least one metal-oxide-semiconductor (MOS) device, the at least one MOS device comprising:
 a semiconductor layer of a first conductivity type;  
 a source region of a second conductivity type formed in the semiconductor layer;  
 a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region;  
 a gate formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions;  
 a buried lightly-doped drain (LDD) region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being formed below at least a portion of the drain region and extending laterally from the drain region to below at least a portion of the gate; and  
 a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer, the second LDD region being self-aligned with a first alignment structure formed substantially concurrently with the gate in a same processing step, the second LDD region being spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.  
 
   
   
     12. The integrated circuit of  claim 11 , wherein the at least one MOS device further comprises a shielding structure formed proximate the upper surface of the semiconductor layer and at least partially between the gate and the drain region, the shielding structure being electrically connected to the source region, the shielding structure being spaced laterally from the gate and being substantially non-overlapping relative to the gate. 
   
   
     13. The integrated circuit of  claim 11 , wherein the at least one MOS device further comprises a second alignment structure formed proximate the upper surface of the semiconductor layer and at least partially between the second LDD region and the drain region, wherein the drain region is self-aligned to a first edge of the alignment structure and the second LDD region is self-aligned with a second edge of the second alignment structure such that the second LDD region is self-aligned with the drain region. 
   
   
     14. The integrated circuit of  claim 11 , wherein the first alignment structure in the at least one MOS device is removed after forming the second LDD region.