Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate

Abstract

A die-attach method and assembly using film and epoxy bonds speeds manufacturing for large die assemblies while providing improved bond characteristics. An adhesive film defining an epoxy flow mask is attached to the die or substrate, epoxy is dispensed within the epoxy flow mask area and the die is then bonded to the substrate. The film controls the flow of the epoxy, preventing spillover. Additionally, the epoxy area can be made small with respect to the die size, reducing the time required to dispense the epoxy and reducing the amount of epoxy material required.

1. A method for manufacturing an integrated circuit substrate, comprising:
 embossing a top side of the substrate with a tool having features defining a reverse image of channels for addition of circuit material; 
 adding circuit material within channels formed by the embossing of the top side of the substrate; 
 embossing a bottom side of the substrate with a second tool having features defining a reverse image of bottom channels for addition of bottom circuit material; and 
 adding circuit material within the bottom channels formed by the embossing of the bottom side of the substrate. 
 
   
   
     2. An integrated circuit manufactured by the method of  claim 1 . 
   
   
     3. The method of  claim 1 , wherein the substrate comprises a top insulating layer and bottom insulating layer bonded on opposite sides of a metal layer, wherein the method further comprises perforating the metal layer prior to bonding the insulating layers to the metal layer. 
   
   
     4. The method of  claim 3 , wherein the perforating is performed by etching the metal layer. 
   
   
     5. The method of  claim 1 , wherein the second tool has features for creating voids through the substrate from the channels to the bottom channels, and wherein the method further comprises depositing circuit material within the voids for electrically connecting circuit material within the channels to circuit material within the bottom channels. 
   
   
     6. The method of  claim 1 , further comprising mounting a flip-chip die having electrical contacts on the bottom side by inserting the electrical contacts within the channels formed by the embossing. 
   
   
     7. The method of  claim 1 , wherein the embossing forms a void through the substrate for insertion of a mounting post, and further comprising:
 mounting a die having a retaining post on a top side of the substrate, by inserting the retaining post through the void; and 
 soldering the retaining post to circuit material on the bottom side of the substrate. 
 
   
   
     8. The method of  claim 1 , wherein the adding is performed by electroplating copper on the top side of the substrate and wherein the method further comprises:
 depositing a resist material on top of areas of the circuit material; and 
 etching the electroplated copper to form an electrical circuit within the areas. 
 
   
   
     9. The method of  claim 1 , wherein the adding is performed by electroplating copper on the top side of the substrate, and wherein the method further comprises:
 plating areas of the electroplated copper with a metal resistant to the etching within areas of the circuit material; and 
 etching the electroplated copper, wherein the electroplated copper is retained under the areas. 
 
   
   
     10. The method of  claim 1 , further comprising providing a homogeneous single sheet of dielectric material, and wherein the embossing embosses the top side of the dielectric material to form the channels. 
   
   
     11. The method of  claim 10 , wherein the embossing embosses channels having sides extending to a plane defining a top surface of the dielectric sheet and a bottom beneath the plane. 
   
   
     12. The method of  claim 11 , wherein the embossing embosses channels having a bottom of the channels located at a second plane substantially above the bottom surface of the dielectric sheet. 
   
   
     13. The method of  claim 12 , further comprising bonding the dielectric sheet to a metal layer prior to the embosssing. 
   
   
     14. The method of  claim 1 , wherein the embossing embosses channels having sides extending to a plane defining a top surface of the substrate and a bottom beneath the plane. 
   
   
     15. The method of  claim 14 , wherein the embossing embosses channels having a bottom of the channels located at a second plane substantially above the bottom surface of the substrate. 
   
   
     16. The method of  claim 1 , wherein the adding comprises applying a gold foil within the channels. 
   
   
     17. The method of  claim 1 , further comprising electrically connecting an integrated circuit die to the circuit material within the channels. 
   
   
     18. The method of  claim 17 , wherein the electrically connecting is performed by adding bonding wires between the circuit material and electrical terminals of the die. 
   
   
     19. The method of  claim 17 , wherein the electrically connecting is performed by directly bonding electrical terminals of the die to the circuit material. 
   
   
     20. The method of  claim 1 , further comprising prior to the embossing, stamping a metal foil to form the reverse image of the channels. 
   
   
     21. The method of  claim 20 , further comprising mounting the stamped metal foil to a tooling plate. 
   
   
     22. A method for manufacturing an integrated circuit, comprising:
 first embossing a top side of a top outer dielectric layer of a substrate with a tool having features defining a reverse image of top channels for addition of circuit material, the top channels having sides extending to a plane defining a top surface of the substrate and a bottom beneath the plane, wherein the bottom of the top channels is located at a second plane substantially above the bottom surface of the top outer dielectric layer; 
 adding circuit material within the channels formed by the embossing; and 
 electrically connecting an integrated circuit die to the circuit material within the channels. 
 
   
   
     23. The method of  claim 22 , further comprising second embossing a bottom side of a bottom outer dielectric layer of the substrate with a tool having features defining a reverse image of bottom channels for addition of circuit material, the bottom channels having sides extending to a third plane defining a bottom surface of the substrate and a bottom beneath the third plane, wherein the top of the bottom channels is located at a second plane substantially below the top surface of the bottom outer dielectric layer; and
 adding bottom circuit material within bottom channels. 
 
   
   
     24. The method of  claim 23 , further comprising providing a homogeneous single sheet of dielectric material, and wherein the first embossing embosses the top side of the dielectric sheet to form the top channels and the second embossing embosses the bottom side of the dielectric sheet to form the bottom channels.