Memory array with byte-alterable capability

Abstract

This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

1. A memory array with byte-alterable capability comprising:
 a plurality of adjacent cells each comprising, 
 a select gate metal oxide semiconductor field effect transistor, MOSFET device, and 
 a split-gate memory cell whose source is connected to the drain of said select gate MOSFET device wherein the gate of said select gate MOSFET device is controlled independently of the gate of said split-gate memory cell, 
 select lines connecting the select gate of the select gate MOSFET device of one of the plurality of adjacent cells to the select gate of the select gate MOSFET device of an adjacent one of the plurality of adjacent cells. 
 
   
   
     2. The memory array with byte-alterable capability of  claim 1  further comprising:
 bit lines which are tied to the drains of said split-gate memory cell. 
 
   
   
     3. The memory array with byte-alterable capability of  claim 1  further comprising:
 source lines which are tied to the sources of said select gate MOSFET devices. 
 
   
   
     4. The memory array with byte-alterable capability of  claim 1  further comprising:
 word lines which are tied to control gates of said split-gate memory cell. 
 
   
   
     5. The memory array with byte-alterable capability of  claim 1  wherein said control gate MOSFET contains a floating gate which is insulated from said control gate by a dielectric insulating material such as silicon dioxide. 
   
   
     6. The memory array with byte-alterable capability of  claim 5  wherein said split-gate memory cell contains a source region which is also the drain for said select gate MOSFET device. 
   
   
     7. The memory array with byte-alterable capability of  claim 5  wherein said control gate MOSFET contains a drain region. 
   
   
     8. The memory array with byte-alterable capability of  claim 5  wherein said control gate MOSFET contains a control gate which is insulated from said floating gate by a dielectric insulating material such as silicon dioxide. 
   
   
     9. The memory array with byte-alterable capability of  claim 5  wherein said control gate contained in the control gate MOSFET device is insulated from said drain of said control gate MOSFET device by a dielectric insulating material. 
   
   
     10. The memory array with byte-alterable capability of  claim 1  wherein said select gate MOSFET contains a select gate which is insulated from said select gate drain region and said selected gate source region by a dielectric insulating material. 
   
   
     11. The memory array with byte-alterable capability of  claim 1  wherein the bits of the bytes have a common source line. 
   
   
     12. The memory array with byte-alterable capability of  claim 11  wherein said source line common to said bytes have a high voltage applied to inhibit erase of said cells of unselected bytes. 
   
   
     13. The memory array with byte-alterable capability of  claim 12  wherein said source lines common to said bytes have a low voltage applied to enable an erase of said cells of selected bytes. 
   
   
     14. The memory array with byte-alterable capability of  claim 13  wherein the erasure of selected bytes requires a high voltage on said selected gates associated with the selected bytes. 
   
   
     15. The memory array with byte-alterable capability of  claim 14  wherein the erasure of selected bytes requires a high voltage on said control gates. 
   
   
     16. The memory array with byte-alterable capability of  claim 11  wherein the programming of selected cells of said selected bytes require high voltage on said select gate, a lower voltage on said control gate and a high voltage on said source line. 
   
   
     17. The memory array with byte-alterable capability of  claim 16  wherein said word lines common to said bytes have a zero voltage applied to inhibit programming of unselected cells.