Adjustable self-aligned air gap dielectric for low capacitance wiring

Abstract

An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.

1. A semiconductor device comprising:
 a first interconnect adjacent a second interconnect on an interconnect level; 
 beneath at least one of the first and second interconnects, an etch stop layer positioned over an underlying via insulator level; 
 spacers formed along adjacent sides of the first and second interconnects; and 
 an air gap formed between the first and second interconnects, the air gap extending above an upper surface of at least one of the first and second interconnects and the air gap extending below a lower surface of the at least one of the first and second interconnects having the etch stop layer beneath by a distance corresponding to a thickness of the etch stop layer, distance between the spacers defining the width of the air gap. 
 
   
   
     2. The semiconductor device of  claim 1  wherein the air gap is self-aligned to the adjacent sides of the first and second interconnects. 
   
   
     3. The semiconductor device of  claim 1  wherein the spacers adjacent the sides of the first and second interconnects comprise silicon dioxide or silicon nitride. 
   
   
     4. The semiconductor device of  claim 1  wherein the etch stop layer comprises silicon carbide. 
   
   
     5. The semiconductor device of  claim 1  wherein the underlying via insulator level comprises silicon dioxide or fluorinated silicon dioxide. 
   
   
     6. The semiconductor device of  claim 1  further including hardmask spacers self-aligned to either side of an upper portion of the air gap, wherein the air gap extends between and below the hardmask spacers. 
   
   
     7. The semiconductor device of  claim 6  wherein the hardmask spacers comprise silicon dioxide or silicon nitride. 
   
   
     8. The semiconductor device of  claim 1  further including at least one insulative layer above the interconnect level and the air gap, and wherein the air gap extends into the insulative layer. 
   
   
     9. The semiconductor device of  claim 8  wherein the at least one insulative layer above the interconnect level and the air gap comprises silicon nitride or silicon carbon nitride as a capping layer for the interconnect and silicon dioxide or fluorinated silicon dioxide as an insulative layer above the capping layer. 
   
   
     10. The semiconductor device of  claim 1  further including hardmask spacers self-aligned to either side of an upper portion of the air gap, and an insulative layer above the interconnect level, the air gap and the hardmask spacers, and wherein the air gap extends between the hardmask spacers and upward into the insulative layer. 
   
   
     11. The semiconductor device of  claim 1 , wherein the first and second interconnects are formed by a damascene or dual damascene process. 
   
   
     12. The semiconductor device of  claim 1 , wherein the first and second interconnects comprise copper, aluminum, tungsten or gold. 
   
   
     13. The semiconductor device of  claim 1  further including, beneath one of the first and second interconnects, an etch stop layer positioned over at least one underlying via insulator level, and below the underlying via insulator, a second interconnect level. 
   
   
     14. The semiconductor device of  claim 13  further including, between the at least one underlying via insulator level and the second interconnect level, a selective metal deposition layer comprising a selective tungsten layer or a selective cobalt tungsten phosphide layer. 
   
   
     15. The semiconductor device of  claim 1  further including, over each of the first and second interconnects, a selective metal deposition layer comprising a selective tungsten layer or a selective cobalt tungsten phosphide layer.