Flash memory process with high voltage LDMOS embedded

Abstract

A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

1. A method of forming an integrated circuit comprising the steps of:
 forming a first structure at a first region of a substrate wherein the first structure comprises a first insulating layer formed on the substrate, and a poly silicon feature formed on the first insulating layer; 
 forming a second insulating layer at a second region of the substrate, the second insulating layer having an opening formed therein; 
 forming a first thick oxide on the poly silicon feature and simultaneously forming a second thick oxide in the opening of the second insulating layer; 
 forming a first conductive feature over at least a portion of the first thick oxide, and simultaneously forming a second conductive feature physically separated from the first conductive feature, wherein the second conductive feature is over a portion of the second insulating layer, and wherein at least one end of the second conductive feature is over a portion of the second thick oxide; 
 forming a first source and a first drain at the first region and a second source and a second drain at the second region; 
 forming a first spacer along a sidewall of the first conductive feature, the polysilicon feature and the first thick oxide; and 
 forming a second spacer along sidewall of the second conductive feature. 
 
   
   
     2. The method of  claim 1  further comprising the steps of:
 forming a drift region at the second region of the substrate; 
 forming a lightly doped drain region adjacent the second drain at the second region; and 
 forming a source sinker region adjacent the second source at the second region. 
 
   
   
     3. The method of  claim 1  wherein the step of forming a first thick oxide on the poly silicon feature and simultaneously forming a second thick oxide in the opening of the second insulating layer comprises:
 forming a first mask layer on the poly silicon feature at the first location; 
 forming a second mask layer on the second insulating layer at the second location; 
 forming a first opening in the first mask layer to expose the poly silicon feature; 
 forming a second opening in the second mask layer and the second insulating layer to expose the substrate; 
 exposing the exposed poly silicon feature and the exposed substrate to an oxygen source; 
 removing the first mask layer; and 
 removing the second mask layer. 
 
   
   
     4. The method of  claim 3  wherein the first mask layer and the second mask layer are the same silicon nitride layer formed at the same time. 
   
   
     5. The method of  claim 1  wherein the first insulating layer and the second insulating layer are the same layer formed at the same time. 
   
   
     6. The method of  claim 5  wherein the first insulating layer and the second insulating layer are formed by thermal oxidation. 
   
   
     7. The method of  claim 1  wherein the first insulating layer has a thickness of about 60 Å to about 110 Å. 
   
   
     8. The method of  claim 1  wherein the substrate comprises silicon. 
   
   
     9. The method of  claim 1  wherein a portion of the first conductive feature is not over the first thick oxide. 
   
   
     10. The method of  claim 1  wherein the first thick oxide and the second thick oxide are formed by local oxidation of silicon (LOCOS). 
   
   
     11. The method of  claim 1  further comprising the step of:
 forming a compound structure at the second region wherein the compound structure comprises the second insulating layer over the substrate and the second conductive feature over the second insulating layer, and wherein the compound structure is not formed on the second thick oxide. 
 
   
   
     12. The method of  claim 11  further comprising the step of patterning the second conductive feature to form a resistor. 
   
   
     13. The method of  claim 12  further comprising the steps of:
 forming a third spacer along a sidewall of the second conductive feature and the second insulating layer; and 
 farming a third source and a third drain region adjacent the third spacer. 
 
   
   
     14. The method of  claim 13  further comprising the step of connecting the third source and the third drain to form a capacitor. 
   
   
     15. A method of forming an integrated circuit comprising the steps of:
 forming a first insulating layer at a first location and a second location of a silicon substrate; 
 forming a poly silicon feature on the first insulating layer at the first location; 
 forming a mask layer over the poly silicon feature and the first insulating layer; 
 forming a first opening in the mask layer at the first location to expose the first poly silicon feature, and forming a second opening in the mask layer and the first insulating layer to expose the silicon substrate at the second location; 
 forming a first thick oxide on the exposed poly silicon feature and in the first opening; 
 forming a second thick oxide on the exposed silicon substrate and in the second opening; 
 selectively removing the poly silicon and the first insulating layer not covered by the first thick oxide; 
 forming a second insulating layer at the first location; 
 forming a conductive layer at the first location and the second location; 
 at the first location, removing portions of the conductive layer and the second insulating layer, such that a remaining conductive layer and a remaining second insulating layer in the first region each have a portion over the first thick oxide; 
 at the second location, removing portions of the conductive layer and the first insulating layer, such that a remaining conductive layer in the second location has at least one end over a portion of the second thick oxide and extending over part of the first insulating layer, wherein the remaining conductive layer in the first location is electrically disconnected from the remaining conductive layer in the second location; 
 forming a source and a drain in the first location of the silicon substrate; 
 forming a spacer along a sidewall of the remaining conductive layer at the first location; and 
 forming a spacer along a sidewall of the remaining conductive layer and the thick oxide at the second location. 
 
   
   
     16. The method of  claim 15  wherein the first opening and the second opening are formed simultaneously. 
   
   
     17. The method of  claim 15  wherein after the step of removing portions of the conductive layer and the second insulating layer, the remaining conductive layer and second insulating layer are coterminous with the poly silicon remaining after the step of selectively removing the poly silicon and the first insulating layer not covered by the thick oxide at the first location. 
   
   
     18. The method of  claim 15  wherein after the step of removing portions of the conductive layer and the second insulating layer, a portion of the remaining conductive layer extends beyond the poly silicon remaining after the step of selectively removing the poly silicon and the first insulating layer not covered by the thick oxide at the first location. 
   
   
     19. The method of  claim 15  wherein the first insulating layer has a thickness of about 60 Å to about 110 Å. 
   
   
     20. The method of  claim 15  wherein the first and the second thick oxides are formed by local oxidation of silicon (LOCOS). 
   
   
     21. The method of  claim 1 , wherein the second conductive feature further comprises a second horizontal portion physically connected to the vertical portion, wherein the second conductive feature is over the poly silicon feature. 
   
   
     22. The method of  claim 1 , wherein after the step of forming the first structure, the second region is free from the poly silicon feature. 
   
   
     23. The method of  claim 1 , wherein the first and the second insulating layers are a same layer. 
   
   
     24. The method of  claim 15 , wherein after the step of forming the poly silicon on the first insulating layer, the second location is free from the poly silicon. 
   
   
     25. A method of forming an integrated circuit comprising the steps of:
 forming a first structure at a first region of a substrate wherein the first structure comprises a first insulating layer formed on the substrate, and a poly silicon feature formed on the first insulating layer; 
 forming a second insulating layer at a second region of the substrate, the second insulating layer having an opening formed therein; 
 forming a first thick oxide on the poly silicon feature and simultaneously forming a second thick oxide in the opening of the second insulating layer; 
 forming a first conductive feature over at least a portion of the first thick oxide, and simultaneously forming a second conductive feature, wherein the first feature has a vertical portion on a sidewall of the poly silicon feature and a sidewall of the first thick oxide, and a horizontal portion extending away from the poly silicon feature, and wherein the first and the second conductive features are physically separated and are each continuous; 
 forming a first source and a first drain at the first region and a second source and a second drain at the second region; 
 forming a first spacer along a sidewall of the first conductive feature, the polysilicon feature and the first thick oxide; end 
 forming a second spacer along a sidewall of the second conductive feature. 
 
   
   
     26. The method of  claim 25  further comprising the steps of:
 forming a drift region at the second region of the substrate; 
 forming a lightly doped drain region adjacent the second drain at the second region; and 
 forming a source sinker region adjacent the second source at the second region. 
 
   
   
     27. The method of  claim 25 , wherein the step of forming a first thick oxide on the poiy silicon feature and simultaneously forming a second thick oxide in the opening of the second insulating layer comprises:
 forming a first mask layer on the poly silicon feature at the first location; 
 forming a second mask layer on the second insulating layer at the second location; 
 forming a first opening in the first mask layer to expose the poly silicon feature; 
 forming a second opening in the second mask layer and the second insulating layer to expose the substrate; 
 exposing the exposed poly silicon feature and the exposed substrate to an oxygen source; 
 removing the first mask layer; and 
 removing the second mask layer.