Method and apparatus for accelerating through-the pins LBIST simulation

Abstract

The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

1. A method for applying external clock patterns and external data patterns for logic built-in self testing (“LBIST”) in a simulator, comprising:
 setting up a simulation model in the simulator for a logic under test; 
 setting up an external LBIST block in the simulation model, wherein the external LBIST block comprises pre-verified internal clock and pre-verified data pattern logic; 
 connecting external clock inputs and external data inputs from the external LBIST block to the logic under test; 
 determining the external clock patterns and the external data patterns to test the logic under test; 
 applying the external clock patterns and the external data patterns to the logic under test; and 
 receiving and processing output patterns from the logic under test, wherein the external LBIST block further comprises: 
 at least one phase shift and spreader block (“PSSB”); 
 at least one pseudo-random pattern generator (“PRPG”); and 
 at least one LBIST controller clock pattern generator, wherein the LBIST controller clock pattern generator is coupled to the at least one PSSB and the at least one PRPG. 
 
   
   
     2. The method of  claim 1 , wherein the step of applying the external clock patterns and the external data patterns comprises applying only the external clock patterns to the logic under test. 
   
   
     3. The method of  claim 1 , wherein the pre-verified internal clock and the pre-verified data pattern logic is the same as logic used for on-product clock generation (“OPCG”). 
   
   
     4. The method of  claim 1 , wherein the at least one PSSB and the at least one PRPG are disabled when only the external clock patterns are provided to the logic under test. 
   
   
     5. The method of  claim 1 , wherein the step of receiving and processing output patterns further comprises configuring a receiver block in the simulation model for receiving and processing the output patterns. 
   
   
     6. The method of  claim 1 , wherein the step of receiving and processing output patterns further comprises:
 scanning the output patterns outside of the simulation model; and 
 processing the output patterns outside of the simulation model.