P
US7420846B2ExpiredUtilityPatentIndex 74

Read and erase verify methods and circuits suitable for low voltage non-volatile memories

Assignee: SANDISK CORPPriority: Apr 14, 2003Filed: Apr 8, 2004Granted: Sep 2, 2008
Est. expiryApr 14, 2023(expired)· nominal 20-yr term from priority
Inventors:CHEN JIANQUADER KHANDKER N
G11C 16/3459G11C 11/5642G11C 11/5628G11C 16/26G11C 16/344G11C 7/04G11C 2211/5621G11C 16/3445G11C 16/20G11C 16/0483G11C 11/5635G11C 16/16G11C 16/10
74
PatentIndex Score
6
Cited by
29
References
14
Claims

Abstract

In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

Claims

exact text as granted — not AI-modified
1. A memory comprising:
 a non-volatile data storage element capable of storing a first data state characterized by a negative threshold voltage and one or more second data states characterized by a positive threshold voltage; and 
 sense circuitry connectable to the data storage element that can distinguish the data state of the storage element, comprising;
 a compensation circuit, whereby a voltage applied to a control gate of the data storage element by the sense circuitry to distinguish between the first and second data states in a normal read process is varied as a continuous function of one or more operating conditions. 
 
 
   
   
     2. The memory of  claim 1 , wherein said operating conditions comprise temperature. 
   
   
     3. The memory of  claim 1 , wherein said operating conditions comprise the voltage level of an external power supply. 
   
   
     4. The memory of  claim 1 , wherein said data storage element is capable of storing a plurality of said second data states. 
   
   
     5. The memory of  claim 1 , wherein said voltage applied to the control gate of the data storage element is in a range of from 0 volts to 0.2 volts. 
   
   
     6. The memory of  claim 1 , further comprising:
 write circuitry connectable to the data storage element and the sense circuitry, wherein the sense circuitry is used for program verify and the verify level for the second data states is compensated based on operating conditions. 
 
   
   
     7. The memory of  claim 1  further comprising:
 a negative voltage source; and 
 a band gap generator connectable to the negative voltage source whereby said voltage applied to the control gate of the data storage element is provided. 
 
   
   
     8. The memory of  claim 7  wherein said band gap generator provides a voltage in the range of 0 volts to 0.2 volts. 
   
   
     9. A method of operating a non-volatile memory, comprising:
 selecting a data storage element storing one of a plurality of data states, said plurality of data states comprising a first data state characterized by a negative threshold voltage and one or more second data states characterized by a positive threshold voltage; providing a control gate voltage, wherein said control gate voltage is varied as a continuous function of one or more operating conditions; and 
 applying said control gate voltage to the selected data storage element to distinguish in a normal read process between the first data states and the second data states. 
 
   
   
     10. The method of  claim 9 , wherein said plurality of data states comprises a plurality of second data states. 
   
   
     11. The method of  claim 9 , wherein said operating conditions comprise temperature. 
   
   
     12. The method of  claim 9 , wherein said operating conditions comprise the voltage level of an external power supply. 
   
   
     13. The method of  claim 9 , wherein said control gate voltage is in the range of 0 volts to 0.2 volts. 
   
   
     14. The method of  claim 9 , further comprising:
 generating a negative voltage, wherein the control gate voltage is produced using said negative voltage.

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