Single-mask phase change memory element

Abstract

A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

What is claimed is: 
     
       1. A memory device, comprising:
 an array of memory elements, formed on a semiconductor chip; 
 a parallel array of word lines, extending in a first direction, connecting each memory element to a first data source; 
 a parallel array of bit lines, extending in a second direction, connecting each memory element to a second data source, the second direction forming an acute angle to the first direction; and 
 wherein the connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases, and wherein the phase change elements lie above the lines in the memory element. 
 
     
     
       2. The device of  claim 1 , wherein the memory material comprises a combination of Ge, Sb, and Te. 
     
     
       3. The memory device of  claim 1 , wherein the phase-change cell comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au. 
     
     
       4. The memory device of  claim 1 , wherein the phase change element has a thickness between 5 and 50 nm. 
     
     
       5. The memory device of  claim 1 , wherein the phase change element has a thickness of less than 10 nm. 
     
     
       6. The memory device of  claim 1 , wherein the phase change element has a thickness between 0.5 and 5 nm. 
     
     
       7. The memory device of  claim 1 , wherein the memory element includes a plurality of successively formed metal layers, and wherein the phase change elements lie above all such metal layers. 
     
     
       8. The memory device of  claim 7 , wherein there are two metal layers. 
     
     
       9. The memory device of  claim 7 , wherein there are three metal layers. 
     
     
       10. A memory device, comprising:
 an array of memory elements, formed on a semiconductor chip, each memory element including a drain electrode; 
 a parallel array of word lines, extending in a first direction, connecting each memory element to a first data source; 
 a parallel array of bit lines, extending in a second direction, connecting each memory element to a second data source at the drain electrode, the second direction forming an acute angle to the first direction; 
 wherein the connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases; and 
 wherein the bit lines, the phase change elements and the drain electrodes all lie on the same level within the semiconductor chip. 
 
     
     
       11. The memory device of  claim 10 , wherein the phase-change cell comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au. 
     
     
       12. The memory device of  claim 10 , wherein each phase change element has a thickness between 5 and 50 nm. 
     
     
       13. The memory device of  claim 10 , wherein each phase change element has a thickness of less than 10 nm. 
     
     
       14. The memory device of  claim 10 , wherein each phase change element has a thickness between 0.5 and 5 nm. 
     
     
       15. The memory device of  claim 10 , wherein the memory element includes a plurality of successively formed metal layers. 
     
     
       16. The memory device of  claim 15 , wherein there are two metal layers. 
     
     
       17. The memory device of  claim 15 , wherein there are three metal layers.