Method of processing a semiconductor wafer for manufacture of semiconductor device

Abstract

A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.

1. A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface, the method comprising:
 forming grooves of a predetermined depth on the second surface of the wafer on which circuit patterns are formed; 
 attaching a first surface of a protective tape to the second surface on which the grooves are formed; 
 attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward; 
 removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips at the grooves, the chips having a second surface on which the circuit patterns are formed; and 
 supplying each chip to a die bonder in an orientation wherein a first surface opposite to the second surface of the chip is facing upward. 
 
     
     
       2. The method of  claim 1 , wherein the supplying each chip to the die bonder comprises attaching a carrier unit to the first surface of the chip and moving the carrier unit to the die bonder. 
     
     
       3. The method of  claim 2 , further comprising:
 placing the chip attached to the carrier unit on a stage so that the second surface of the chip can face lead frames on the stage; and 
 attaching the second surface of the chip to the lead frames. 
 
     
     
       4. The method of  claim 3 , wherein the attaching the second surface of the chip to the lead frames is performed by a compression process using a compression unit. 
     
     
       5. The method of  claim 4 , wherein the compression process using the compression unit is performed a plural number of times to include partial compression and complete compression. 
     
     
       6. The method of  claim 3 , wherein the placing the chip attached to the carrier unit on the stage comprises analyzing the circuit patterns formed on the second surface of the chip and aligning the chip in a proper position and orientation on the stage. 
     
     
       7. The method of  claim 3 , wherein the placing the chip attached to the carrier unit on the stage comprises recognizing edges of the chip and aligning the chip in a proper position and orientation on the stage. 
     
     
       8. The method of  claim 1 , wherein the supplying each chip to the die bonder comprises aligning the chip and placing the chip in a proper position and orientation on the die bonder. 
     
     
       9. The method of  claim 8 , wherein the aligning the chip is performed by sensing at least three recognition points on the second surface of the chip. 
     
     
       10. The method of  claim 1 , wherein data representing a position on a first surface of the wafer of any one or more failed chips are stored in a data server, which method further comprises:
 converting the data by mapping the position in such manner as to create converted data representing a converted position on a second surface of the wafer opposite to the first surface of the one or more failed chips.