Access transistor for memory device

Abstract

An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

The invention claimed is: 
     
       1. A memory array comprising:
 a substrate; 
 a plurality of access transistors over the substrate, each access transistor comprising a channel region between first and second electrodes, the channel region, first electrode and second electrode being vertically stacked over the substrate, the channel region being in contact with a top surface of the first electrode and completely isolated from the substrate by the first electrode; and 
 a resistance variable material and a first portion of metal-chalcogenide material over and electrically coupled to a plurality of second electrodes of respective access transistors and forming a plurality of resistance variable memory elements, each accessed by the respective access transistor, wherein the channel region comprises a second portion of the metal-chalcogenide material. 
 
     
     
       2. The array of  claim 1 , wherein the access transistor further comprises a gate, and wherein the gate is a conductive line. 
     
     
       3. The array of  claim 2 , wherein the channel region comprises a semi-conductive material extending through the conductive line and being in contact with the first electrode. 
     
     
       4. The array of  claim 3 , wherein the second electrode is an electrode for the at least one memory element. 
     
     
       5. The array of  claim 3 , wherein the semi-conductive material is laterally surrounded by the conductive line. 
     
     
       6. The array of  claim 3 , wherein the semi-conductive material is only partially laterally surrounded by the conductive line. 
     
     
       7. The array of  claim 1 , wherein the channel region comprises a semi-conductive material within a via. 
     
     
       8. The array of  claim 7 , wherein sidewalls of the via are lined with an insulating layer. 
     
     
       9. The memory array of  claim 1 , wherein the resistance variable material is in contact with at least a portion of the second electrode of each respective access transistor. 
     
     
       10. A processor system, the system comprising:
 a processor; and 
 a memory device coupled to the processor, the memory device comprising a memory array, the memory array comprising: 
 a plurality of transistors, each transistor comprising a channel region between first and second source/drain regions, the channel region, first source/drain region and second source/drain region being vertically stacked over the substrate, the first source/drain region being a first conductive line, the conductive line being completely isolated from a substrate by a dielectric region, the channel region being in contact with a top surface of the first conductive line, and 
 a plurality of blanket layers stacked over and electrically coupled to a plurality of second source/drain regions of respective transistors and forming a plurality of memory elements, 
 each accessed by the respective transistor, the plurality of layers comprising a resistance variable material and a metal-chalcogenide material, wherein the channel region comprises the metal-chalcogenide material. 
 
     
     
       11. The system of  claim 10 , wherein the access transistor further comprises a gate and the gate is a second conductive line. 
     
     
       12. The system of  claim 11 , and wherein the channel region comprises a semi-conductive material extending through the second conductive line and is in contact with the first conductive line, and wherein the second source/drain region is a conductive layer in contact with the channel region. 
     
     
       13. The system of  claim 12 , wherein the conductive layer is the first electrode.