P
US7600135B2ExpiredUtilityPatentIndex 92

Apparatus and method for software specified power management performance using low power virtual threads

Assignee: MIPS TECH INCPriority: Apr 14, 2005Filed: Apr 14, 2005Granted: Oct 6, 2009
Est. expiryApr 14, 2025(expired)· nominal 20-yr term from priority
Inventors:JONES DARREN M
G06F 9/3888G06F 9/3851G06F 9/3009G06F 9/3842Y02D10/00G06F 9/3863G06F 1/32G06F 9/4893G06F 9/30087G06F 1/3203
92
PatentIndex Score
19
Cited by
32
References
22
Claims

Abstract

A processor comprises a software control module specifying a power performance metric. A policy manager is responsive to the software control module. A dispatch scheduler is responsive to the policy manager to operate the processor in accordance with the power performance metric.

Claims

exact text as granted — not AI-modified
1. A processor, comprising:
 a software control module specifying a power performance metric; 
 a policy manager responsive to said software control module; and 
 a dispatch scheduler responsive to said policy manager to operate said processor in accordance with said power performance metric; 
 wherein said dispatch scheduler is within the core of said processor and said policy manager is a customizable multi-thread scheduling unit outside the core of said processor; 
 wherein said policy manager specifies a low power virtual thread responsive to said power performance metric, said dispatch scheduler scheduling said low power virtual thread but never selecting said low power virtual thread; 
 wherein said policy manager instructs selected threads to be shut down in response to said power performance metric and said dispatch scheduler shuts down said selected threads. 
 
     
     
       2. The processor of  claim 1  wherein said power performance metric is an instructions per unit time parameter. 
     
     
       3. The processor of  claim 1  wherein said policy manager tracks the operation of said low power virtual thread. 
     
     
       4. The processor of  claim 1  wherein said dispatch scheduler specifies that no operations are performed in pipeline positions corresponding to pipeline positions of said low power virtual thread. 
     
     
       5. A processor, comprising:
 a software control module specifying a power performance metric; 
 a policy manager responsive to said software control module; and 
 a dispatch scheduler responsive to said policy manager to operate said processor in accordance with said power performance metric; 
 wherein said dispatch scheduler is within the core of said processor and said policy manager is a customizable multi-thread scheduling unit outside the core of said processor; 
 wherein said policy manager instructs selected threads to be shut down in response to said power performance metric and said dispatch scheduler shuts down said selected threads. 
 
     
     
       6. The processor of  claim 5  wherein said policy manager instructs selected threads to be shut down on a cycle-by-cycle basis. 
     
     
       7. A processor, comprising:
 a software control module specifying a power performance metric; 
 a bifurcated thread scheduler including a multi-thread internal processor core component and a customizable multi-thread external processor core component in direct communication with said software control module, said bifurcated thread scheduler operating said processor in accordance with said power performance metric; 
 wherein said customizable multi-thread external processor core component specifies a low power virtual thread responsive to said power performance metric, said multi-thread internal processor core component scheduling said low power virtual thread but never selecting said low power virtual thread. 
 
     
     
       8. The processor of  claim 7  wherein said power performance metric is an instructions per unit time parameter. 
     
     
       9. The processor of  claim 7  wherein said customizable multi-thread external processor core component tracks the operation of said low power virtual thread. 
     
     
       10. The processor of  claim 7  wherein said multi-thread internal processor core component specifies that no operations are performed in pipeline positions corresponding to pipeline positions of said low power virtual thread. 
     
     
       11. A processor, comprising:
 a software control module specifying a power performance metric; 
 a bifurcated thread scheduler including a multi-thread internal processor core component and a customizable multi-thread external processor core component in direct communication with said software control module, said bifurcated thread scheduler operating said processor in accordance with said power performance metric; 
 wherein said customizable multi-thread external processor core component instructs selected threads to be shut down in response to said power performance metric and said multi-thread internal processor core shuts down said selected threads. 
 
     
     
       12. The processor of  claim 11  wherein said customizable multi-thread external processor core component instructs selected threads to be shut down on a cycle-by-cycle basis. 
     
     
       13. A method of operating a processor, comprising:
 specifying a power performance metric via software control; 
 responding to said power performance metric at a customizable multi-thread external processor core component; and 
 implementing said power performance metric with a multi-thread internal processor core component responsive to said customizable multi-thread external processor core component; 
 wherein responding includes specifying a low power virtual thread responsive to said power performance metric, and implementing includes scheduling said low power virtual thread but never selecting said low power virtual thread. 
 
     
     
       14. The method of  claim 13  wherein specifying includes specifying an instructions per unit time parameter. 
     
     
       15. The method of  claim 13  further comprising stopping operations in pipeline positions corresponding to pipeline positions of said low power virtual thread. 
     
     
       16. A method of operating a processor, comprising:
 specifying a power performance metric via software control; 
 responding to said power performance metric at a customizable multi-thread external processor core component; and 
 implementing said power performance metric with a multi-thread internal processor core component responsive to said customizable multi-thread external processor core component; 
 wherein responding includes instructing selected threads to be shut down in response to said power performance metric, wherein responding includes instructing selected threads to be shut down on a cycle-by-cycle basis. 
 
     
     
       17. A computer readable storage medium, comprising executable instructions to:
 define a policy manager responsive to a power performance metric from a software control module, wherein said policy manager is a customizable multi-thread scheduling unit outside the core of a processor; and 
 specify a dispatch scheduler within said core of said processor to be responsive to said policy manager to operate in accordance with said power performance metric; 
 wherein said executable instructions to define a policy manager include executable instructions to specify a low power virtual thread responsive to said power performance metric, and wherein said executable instructions to specify a dispatch scheduler include executable instructions to specify a dispatch scheduler to schedule said low power virtual thread but never select said low power virtual thread. 
 
     
     
       18. The computer readable storage medium of  claim 17  wherein said executable instructions to define a policy manager include executable instructions to define a policy manager that tracks the operation of said low power virtual thread. 
     
     
       19. The computer readable storage medium of  claim 17  wherein said executable instructions to specify a dispatch scheduler include executable instructions to specify a dispatch scheduler that specifies that no operations are performed in pipeline positions corresponding to pipeline positions of said low power virtual thread. 
     
     
       20. A method of enabling a computer to generate a processor, comprising:
 selecting executable instructions that
 define a policy manager responsive to a power performance metric from a software control module, wherein the policy manager is a customizable multi-thread scheduling unit outside the core of said processor; and 
 specify a dispatch scheduler responsive to said policy manager to operate a processor in accordance with said power performance metric, wherein said dispatch scheduler is within the core of said processor; and 
 
 transmitting said executable instructions over a network to a designated computer; 
 wherein selecting executable instructions includes selecting executable instructions that define a policy manager that specifies a low power virtual thread responsive to said power performance metric, and wherein selecting executable instructions includes selecting executable instructions that specify a dispatch scheduler to schedule said low power virtual thread but never select said low power virtual thread. 
 
     
     
       21. The method of  claim 20  wherein selecting executable instructions includes selecting executable instructions to define a policy manager that tracks the operation of said low power virtual thread. 
     
     
       22. The method of  claim 20  wherein selecting executable instructions includes selecting executable instructions to specify a dispatch scheduler that specifies that no operations are performed in pipeline positions corresponding to pipeline positions of said low power virtual thread.

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