Split gate non-volatile memory devices and methods of forming the same

Abstract

Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

1. A split-gate memory cell, comprising:
 first and second diffusion regions formed in a semiconductor substrate; 
 a floating gate electrode formed on the semiconductor substrate between the first and second diffusion regions, wherein a first side of the floating gate electrode overlaps a portion of the first diffusion region; 
 a control gate electrode formed on the semiconductor substrate between a second side of the floating gate electrode and the second diffusion region; 
 a tunneling dielectric layer disposed between the control gate electrode and the second side of the floating gate electrode; 
 a coupling gate electrode formed on the first diffusion region in the semiconductor substrate and adjacent to the first side of the floating gate electrode to overlap at least a portion of an upper surface of the floating gate electrode; and 
 a coupling dielectric layer disposed between the coupling gate electrode and the first side of the floating gate electrode and between the coupling gate electrode and the portion of the upper surface of the floating gate electrode, wherein a thickness of the coupling dielectric layer is less than a thickness of the tunneling dielectric layer. 
 
   
   
     2. The memory cell of  claim 1 , wherein the tunneling dielectric layer has a thickness in a range of about 90 angstroms to about 300 angstroms. 
   
   
     3. The memory cell of  claim 1 , wherein the coupling dielectric layer has a thickness in a range of about 40 angstroms to about 100 angstroms. 
   
   
     4. The memory cell of  claim 1 , wherein the second side of the floating gate electrode forms a tip-shaped structure. 
   
   
     5. The memory cell of  claim 1 , wherein the coupling gate electrode is connected to a power supply line. 
   
   
     6. The memory cell of  claim 1 , wherein the first diffusion region comprises a heavily doped diffusion region and a lightly doped diffusion region. 
   
   
     7. The memory cell of  claim 6 , further comprising a third diffusion region surrounding the lightly doped diffusion region. 
   
   
     8. The memory cell of  claim 1 , further comprising an insulation layer formed between an upper surface of the floating gate electrode and the tunneling dielectric layer. 
   
   
     9. The memory cell of  claim 1 , wherein the tunneling dielectric layer comprises a stack of dielectric layers. 
   
   
     10. The memory cell of  claim 1 , wherein the tunneling dielectric layer is formed by a first dielectric layer and a second dielectric layer, and the coupling dielectric layer is formed by the second dielectric layer.