Transistor, memory cell, memory cell array and method of forming a memory cell array

Abstract

One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

1. An integrated circuit including a transistor comprising:
 a channel region disposed in a semiconductor substrate between a first and a second source/drain region, wherein the first and the second source/drain region are formed adjacent to an upper surface of the semiconductor substrate and wherein the channel region has horizontal and vertical components with respect to the upper surface of the semiconductor substrate; 
 a gate groove formed in the upper surface of the semiconductor substrate adjacent to the channel region, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion; and 
 sidewall spacers made of an insulating material, 
 wherein the lower portion of the gate groove is filled with polysilicon and a metal or a metal compound is disposed in the upper portion of the gate groove, thereby forming a gate electrode; 
 wherein an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate; and 
 wherein the sidewall spacers are disposed on the sidewalls of the upper portion of the gate groove, a bottom side of the sidewall spacers being disposed above an upper side of the lower portion of the gate groove. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein a bottom side of the sidewall spacers is at the same height as the interface between the lower portion of the gate groove and the metal or metal compound. 
     
     
       3. The integrated circuit of  claim 1 , wherein the channel region comprises a fin-region in which the channel region has the shape of a ridge, the ridge comprising a top side and two lateral sides in a cross section perpendicular to a channel direction being defined by a line connecting the first and the second source/drain regions, wherein the top side is disposed beneath the upper surface of the semiconductor substrate and wherein in a cross section perpendicular to the channel direction the gate electrode is disposed along the top side and the two lateral sides of the channel region. 
     
     
       4. The integrated circuit of  claim 1 , wherein a portion of the metal or metal compound is disposed above the upper surface of the substrate. 
     
     
       5. An integrated circuit including a transistor comprising:
 a channel region disposed in a semiconductor substrate between a first and a second source/drain region, wherein the first and the second source/drain region are formed adjacent to an upper surface of the semiconductor substrate and wherein the channel region has horizontal and vertical components with respect to the upper surface of the semiconductor substrate; and 
 a gate groove formed in the upper surface of the semiconductor substrate adjacent to the channel region, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion; 
 wherein the lower portion of the gate groove is filled with polysilicon and a metal or a metal compound is disposed in the upper portion of the gate groove, thereby forming a gate electrode; 
 wherein an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate; and 
 wherein a distance between a bottom side of the gate groove to the upper surface of the substrate is larger than a distance between a bottom side of the first and second source/drain regions and the upper surface of the substrate, respectively. 
 
     
     
       6. The integrated circuit of  claim 5 , wherein the channel region comprises a horizontal component. 
     
     
       7. The integrated circuit of  claim 5 , wherein the gate electrode is electrically connected to a metal conductive line by a layer stack comprising a metal layer. 
     
     
       8. The integrated circuit of  claim 5 , wherein a portion of the metal or metal compound is disposed above the upper surface of the substrate. 
     
     
       9. The integrate circuit of  claim 5 , wherein the channel region comprises a fin-region in which the channel region has the shape of a ridge, the ridge comprising a top side and two lateral sides in a cross section perpendicular to a channel direction being defined by a line connecting the first and the second source/drain regions, wherein the top side is disposed beneath the upper surface of the semiconductor substrate and wherein in a cross section perpendicular to the channel direction the gate electrode is disposed along the top side and the two lateral sides of the channel region. 
     
     
       10. The integrated circuit of  claim 9 , further comprising sidewall spacers made of an insulating material and being formed on sidewalls of the gate groove. 
     
     
       11. The integrated circuit of  claim 10 , wherein the sidewall spacers are disposed on the sidewalls of the upper portion of the gate groove, a bottom side of the sidewall spacers being disposed above an upper side of the lower portion of the gate groove. 
     
     
       12. The integrated circuit of  claim 5 , further comprising sidewall spacers made of an insulating material and formed on sidewalls of the gate groove. 
     
     
       13. The integrated circuit of  claim 12 , wherein a bottom side of the sidewall spacers is at the same height as the interface between the lower portion of the gate groove and the metal or metal compound. 
     
     
       14. The integrated circuit of  claim 12 , wherein the sidewall spacers are disposed on the sidewalls of the upper portion of the gate groove, a bottom side of the sidewall spacers being disposed above an upper side of the lower portion of the gate groove. 
     
     
       15. The integrated circuit of  claim 14 , wherein a material of the upper portion of the gate groove comprises at least one selected from the group consisting of Ti, TiN, WN and W. 
     
     
       16. The integrated circuit of  claim 15 , wherein the metal or metal compound is formed as a conformally deposited layer. 
     
     
       17. An integrated circuit including a memory cell comprising:
 a storage capacitor comprising a storage electrode, a counter electrode and a capacitor dielectric disposed between the storage electrode and the counter electrode; and 
 a transistor comprising:
 a channel region disposed in a semiconductor substrate between a first and second source/drain regions, wherein the first and the second source/drain region are formed adjacent to an upper surface of the semiconductor substrate and wherein the channel region has horizontal and vertical components with respect to the upper surface of the semiconductor substrate; and 
 a gate groove formed in the upper surface of the semiconductor substrate adjacent to the channel region, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion; 
 a gate dielectric layer disposed between the channel region and the gate groove, 
 wherein the lower portion of the gate groove is filled with polysilicon and a metal or a metal compound is disposed in the upper portion of the gate groove, thereby forming a gate electrode; 
 wherein an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate; 
 wherein a distance between a bottom side of the gate groove to the upper surface is larger than a distance between a bottom side of the first and second source/drain regions and the upper surface, respectively; and 
 wherein the first source/drain region is connected with the storage electrode of said memory cell. 
 
 
     
     
       18. The integrated circuit of  claim 17 , wherein the channel region comprises a fin-region in which the channel region has the shape of a ridge, the ridge comprising a top side and two lateral sides in a cross section perpendicular to the channel direction being defined by a line connecting said first and second source/drain regions, wherein the top side is disposed beneath the upper surface of the semiconductor substrate and wherein in a cross section perpendicular to the channel direction the gate electrode is disposed along the top side and the two lateral sides of the channel region. 
     
     
       19. The integrated circuit of  claim 17 , wherein a portion of the metal or metal compound is disposed above the upper surface of the substrate. 
     
     
       20. The integrated circuit of  claim 17 , wherein the transistor further comprises sidewall spacers made of an insulating material and formed on sidewalls of the gate groove. 
     
     
       21. The integrated circuit of  claim 20 , wherein the sidewall spacers are disposed on the sidewalls of the upper portion of the gate groove, a bottom side of the sidewall spacers being disposed above an upper side of the lower portion of the gate groove. 
     
     
       22. A method of forming an integrated circuit comprising a memory cell comprising:
 forming a plurality of storage capacitors for storing information; 
 forming a plurality of first and a second source/drain regions in the semiconductor substrate adjacent to an upper surface of the semiconductor substrate, a channel formed between each of the first and a corresponding one of the second source/drain regions, wherein the channel has horizontal and vertical components with respect to the upper surface of the semiconductor substrate and wherein each of the first source/drain regions connected with a storage electrode of a corresponding one of the storage capacitors, 
 forming a plurality of gate electrodes, 
 wherein providing the gate electrode comprises:
 forming a gate groove in the upper surface of the substrate so that finally a gate groove extends from the upper surface of the semiconductor substrate in a direction perpendicular to the upper surface of the semiconductor substrate, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion, a distance between a bottom side of the gate groove to the upper surface being larger than a distance between a bottom side of the first and second source/drain regions and the upper surface, respectively; 
 forming a gate dielectric at an interface between the semiconductor substrate and the gate groove; and 
 filling the lower portion of the gate groove with polysilicon and forming a metal or a metal compound in the upper portion of the gate groove such that an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate. 
 
 
     
     
       23. The method of  claim 22 , wherein defining a gate groove in said substrate further comprises depositing a silicon dioxide layer on the substrate surface, defining an opening in the silicon dioxide layer and, subsequently, etching the substrate material taking the silicon dioxide layer as a hard mask. 
     
     
       24. The method of  claim 22 , wherein the metal or metal compound is formed by a conformal deposition method. 
     
     
       25. An integrated circuit comprising:
 a peripheral portion comprising a conductive line; and 
 an array portion comprising memory cells, the peripheral portion and the array portion being disposed in different portions of a semiconductor substrate, respectively, 
 individual ones of the memory cells comprising a transistor which is at least partially formed in the semiconductor substrate, the transistor comprising: 
 a channel region disposed in the semiconductor substrate between a first and a second source/drain region, wherein the first and the second source/drain region are formed adjacent to an upper surface of the semiconductor substrate and wherein the channel region has horizontal and vertical components with respect to the upper surface of the semiconductor substrate; 
 a gate groove formed in the semiconductor substrate adjacent to the channel region, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion; and 
 a gate dielectric layer disposed between the channel region and the gate groove, 
 wherein the lower portion of the gate groove is filled with polysilicon and a metal or a metal compound is disposed in the upper portion of the gate groove, thereby forming an array gate electrode; and 
 wherein an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate; 
 wherein the conductive line of the peripheral portion comprises the metal or the metal compound comprised by the array gate electrode.