Method for manufacturing package on package with cavity

Abstract

A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.

1. A method for manufacturing a package on package with a cavity, the method comprising:
 forming a first upper substrate cavity in a lower side of an upper substrate; 
 forming a second upper substrate cavity in an upper side of the upper substrate; 
 mounting an upper semiconductor chip in the second upper substrate cavity of the upper substrate; 
 forming a lower substrate cavity in an upper side of a lower substrate; 
 mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate such that a lower portion of the lower semiconductor chip is accommodated in the lower substrate cavity; and 
 stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. 
 
     
     
       2. A method for manufacturing a package on package with a cavity, the method comprising:
 forming a hole in an upper substrate such that the hole penetrates the upper substrate; 
 mounting a semiconductor chip on one opening of the hole formed in an upper side of the upper substrate; 
 forming a lower substrate cavity in an upper side of a lower substrate; 
 mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate such that a lower portion of the lower semiconductor chip is accommodated in the lower substrate cavity; and 
 stacking the upper substrate above the lower substrate such that the hole formed in the upper substrate accommodates a part of the lower semiconductor chip. 
 
     
     
       3. The method of  claim 1 , further comprising forming a solder ball on the lower substrate such that the upper substrate and the lower substrate are electrically combined with the solder ball. 
     
     
       4. The method of  claim 2 , further comprising forming a solder ball on the lower substrate such that the upper substrate and the lower substrate are electrically combined with the solder ball. 
     
     
       5. A method for manufacturing a package on package with a cavity, the method comprising:
 forming a first upper substrate cavity in a lower side of an upper substrate; 
 mounting an upper semiconductor chip on an upper side of the upper substrate; 
 forming a lower substrate cavity in an upper side of a lower substrate; 
 mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate such that a lower portion of the lower semiconductor chip is accommodated in the lower substrate cavity; and 
 stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. 
 
     
     
       6. The method of  claim 5 , further comprising forming a solder ball on the lower substrate such that the upper substrate and the lower substrate are electrically combined with the solder ball.