FinFET transistor and circuit

Abstract

A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

1. A method for tuning the drive strength of an electronic device, comprising:
 forming a source and a drain in a single-crystal material; 
 forming a single-crystal first fin from said single-crystal material, said first fin having first and second opposing ends and first and second opposing sidewalls and extending along a first longitudinal axis from said first to said second end of said first fin, said first end of said first fin in contact with said source and said second end of said first fin in contact with said drain; 
 aligning said first longitudinal axis to a crystal-plane of said single-crystal material; 
 forming a single-crystal second fin from said single-crystal material, said second fin having first and second opposing ends and first and second opposing sidewalls and extending along a second longitudinal axis from said first to said second end of said second fin, said first end of said second fin in contact with said source and said second end of said second fin in contact with said drain; 
 aligning said second longitudinal axis to a plane rotated away from said crystal plane; and 
 forming a single conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said first fin and on said first and second sidewalls of said second fin. 
 
     
     
       2. The method of  claim 1 , wherein said crystal plane has orthogonal first and second axes, said plane has orthogonal first and second axes and said first axis of said crystal plane and said first axis of said plane are mutually parallel. 
     
     
       3. The method of  claim 1 , wherein said source and said drain are doped N-type, said first fin and said second fin independently comprise P-doped, lightly N-doped or intrinsic mono-crystalline silicon, said crystal plane is a {100} crystal-plane and said plane is rotated toward a {110} crystal-plane. 
     
     
       4. The method of  claim 1 , wherein said source and said drain are doped P-type, said first fin and said second fin independently comprise N-doped, lightly P-doped or intrinsic mono-crystalline silicon, said crystal-plane is a {110} crystal-plane and said plane is rotated toward a {100} crystal-plane. 
     
     
       5. The method of  claim 1 , wherein said device has a drive strength, said drive strength being a function of an angle between said first longitudinal axis and said second longitudinal axis. 
     
     
       6. The method of  claim 1 , wherein a mobility of inversion carriers along said first longitudinal axis is greater than a mobility of inversion carriers along said second longitudinal axis. 
     
     
       7. The method of  claim 1 , further including:
 forming a single-crystal third fin from said single-crystal material, said third fin having first and second opposing ends and first and second opposing sidewalls and extending along said first longitudinal axis from said first to said second end of said third fin, said first end of said third fin in contact with said source and said second end of said third fin in contact with said drain; 
 forming said gate dielectric on said first and second sidewalls of said third fin; and 
 forming said conductive gate in contact with said gate dielectric formed on said first and second sidewalls of said third fin. 
 
     
     
       8. The method of  claim 7 , wherein said third fin is positioned between said first fin and said second fin. 
     
     
       9. A method for tuning the drive strength of an electronic device, comprising:
 providing a source and a drain; 
 providing a single-crystal first fin having first and second opposing ends and first and second opposing sidewalls, said first end of said first fin in contact with said source and said second end of said first fin in contact with said drain; 
 providing a single-crystal second fin having first and second opposing ends and first and second opposing sidewalls, said first end of said second fin in contact with said source and said second end of said second fin in contact with said drain; 
 providing a first conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said first fin and on said first sidewall of said second fin; 
 providing a second conductive gate in contact with a gate dielectric formed on said second sidewall of said second fin; and 
 connecting said first gate to a first voltage source at a first voltage level and connecting said second gate a second voltage source at a second voltage level, said first and second voltage levels being different. 
 
     
     
       10. The method of  claim 9 , wherein said first and second voltage levels have different magnitudes, different polarities or both different magnitudes and polarities. 
     
     
       11. The method of  claim 9 , where said drive strength is a function of a magnitude and polarity of said second voltage source. 
     
     
       12. The method of  claim 9 , wherein said source and said drain are doped N-type, said first fin and said second fin comprise intrinsic, lightly N-doped or P-doped mono-crystalline silicon and wherein said first and said second fins are aligned in a direction from respective said first ends of said first and said second fins to respective said second ends of said first and said second fins to a {100} crystal-plane. 
     
     
       13. The method of  claim 9 , wherein said source and said drain are doped P-type, said first fin and said second fin independently comprise intrinsic, N-doped or lightly P-doped mono-crystalline silicon and wherein said first and said second fins are aligned in a direction from respective said first ends of said first and said second fins respective said second ends of said first and said second fins to a {110} crystal-plane. 
     
     
       14. A method of tuning the drive strength ratio between a first transistor and a second transistor in an integrated circuit, comprising:
 providing said transistor, said first transistor comprising:
 a first source and a first drain; 
 a single-crystal first fin having first and second opposing ends and first and second opposing sidewalls, said first end of said first fin in contact with said first source and said second end of said first fin in contact with said first drain; 
 a single-crystal second fin having first and second opposing ends and first and second opposing sidewalls, said first end of said second fin in contact with said first source and said second end of said second fin in contact with said first drain; 
 a first conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said first fin and on said first sidewall of said second fin; and 
 a second conductive gate in contact with a gate dielectric formed on said second sidewall of said second fin; 
 
 providing said second transistor, said second transistor comprising:
 a second source and a second drain; 
 a single-crystal third fin having first and second opposing ends and first and second opposing sidewalls, said first end of said third fin in contact with said second source and said second end of said third fin in contact with said second drain; and 
 a third conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said third fin and on said first and second sidewall of said third fin; and 
 
 connecting said first gate to a first voltage source at a first voltage level and connecting said second gate to a second voltage source at a second voltage level, said first and second voltage levels being different. 
 
     
     
       15. The method of  claim 14 , wherein said first and second voltage levels have different magnitudes, different polarities or both different magnitudes and polarities. 
     
     
       16. The method of  claim 14 , where said drive strength is a function of a magnitude and polarity of said second voltage source. 
     
     
       17. The method of  claim 14  wherein said first source and said first drain are doped N-type said second source and said second drain are doped P-type, said first fin and said second fin independently comprise intrinsic, lightly N-doped or P-doped mono-crystalline silicon and said third fin comprises intrinsic, N-doped or lightly P-doped mono-crystalline silicon. 
     
     
       18. The method of  claim 17 , wherein first and second fins are aligned in a direction from respective said first ends of said first and said second fins to respective said second ends of said first and said second fins to a {100} crystal-plane and said third fin is aligned in a direction from said first end to said second end of said third fin to a {110} crystal-plane. 
     
     
       19. The method of  claim 14 , wherein said first source and said first drain are doped P-type, said second source and said second drain are doped N-type, said first fins and said second fin independently comprise intrinsic, N-doped or lightly P-doped mono-crystalline silicon and said third fin comprises intrinsic, lightly N-doped or P-doped mono-crystalline silicon. 
     
     
       20. The method of  claim 19 , wherein first and second fins are aligned in a direction from respective said first ends of said first and said second fins to said second ends of said first and said second fins to a {110} crystal-plane and said third fin is aligned in a direction from said first end to said second end of said third fin to a {100} crystal-plane.