Semiconductor device

Abstract

Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

1. A semiconductor device comprising:
 memory cells each of which comprises: a source diffusion layer and a drain diffusion layer formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and a gate section that is formed by stacking a charge storage film and a gate electrode via an insulation film on an area of said semiconductor substrate sandwiched between said source diffusion layer and said drain diffusion layer; and 
 control circuitry coupled to said memory cells to control operations of said memory cells, 
 wherein said control circuitry is constructed and performs control such that in an erase operation, holes are supplied from said gate electrode to said charge storage film, and electrons stored in said charge storage film and holes supplied from the gate electrode combine and disappear, and such that before erase and write operation of memory cells, the memory cells subject to said erase and write operation are written, and then said memory cells are erased, and 
 wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell. 
 
     
     
       2. A semiconductor device comprising:
 subblocks in each of which memory cells are disposed, each of the memory cells comprising: a source diffusion layer and a drain diffusion layer formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and a gate section that is formed by stacking a charge storage film and a gate electrode via an insulation film on an area of said semiconductor substrate sandwiched between said source diffusion layer and said drain diffusion layer; and 
 control circuitry coupled to said memory cells to control operations of said memory cells, 
 wherein said control circuitry is constructed and performs control such that before rewriting said memory cells, a write operation is performed by injecting electrons into all the memory cells subject to an erase and write operation in said subblocks, and then an erase operation is performed by supplying holes from said gate electrode to said charge storage film, 
 wherein electrons stored in said charge storage film and holes supplied from said gate electrode combine and disappear, and 
 wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell. 
 
     
     
       3. The semiconductor device according to  claim 1 , wherein each said memory cell is a charge trapping memory cell having a MONOS or MNOS structure including a nitride charge trapping layer, and wherein said control circuitry is constructed and performs control such that said charge trapping memory cell is written by injecting electrons from said semiconductor substrate through said insulation film into said charge trapping memory cell. 
     
     
       4. The semiconductor device according to  claim 2 , wherein each said memory cell is a charge trapping memory cell having a MONOS or MNOS structure including a nitride charge trapping layer, and wherein said control circuitry is constructed and performs control such that said charge trapping memory cell is written by injecting electrons from said semiconductor substrate through said insulation film into said charge trapping memory cell. 
     
     
       5. The semiconductor device according to  claim 1 , wherein said control circuitry is constructed and performs control such that each said memory cell is written by electron injection using hot electrons. 
     
     
       6. The semiconductor device according to  claim 2 , wherein said control circuitry is constructed and performs control such that each said memory cell is written by electron injection using hot electrons. 
     
     
       7. The semiconductor device according to  claim 1 , wherein, in the case of the erase of a memory cell, a read current of the memory cell is detected and the erase is stopped in response to a detection that the read current reaches a predetermined value corresponding to said predetermined threshold level. 
     
     
       8. The semiconductor device according to  claim 2 , wherein, in the case of the erase of a memory cell, a read current of the memory cell is detected and the erase is stopped in response to a detection that the read current reaches a predetermined value corresponding to said predetermined threshold level. 
     
     
       9. A semiconductor device comprising:
 memory cells each of which comprises: a first impurity doped region and a second impurity doped region formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and gate section that is formed by stacking a charge storage film and an electrode via an insulation film on an area of said semiconductor substrate sandwiched between said first impurity doped region and said second impurity doped region; and 
 control circuitry coupled to said memory cells to control operations of said memory cells, 
 wherein said control circuitry is constructed and performs control such that in an erase operation, holes are supplied from said electrode to said charge storage film, and electrons stored in said charge storage film and holes supplied from the electrode combine and disappear, and such that an erase command of said memory cells is executed after writing memory cells subject to said erase, and 
 wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell. 
 
     
     
       10. A semiconductor device comprising:
 subblocks in each of which memory cells are disposed, each of the memory cells comprising: a source diffusion layer and a drain diffusion layer formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and a gate section that is formed by stacking a charge storage film and a gate electrode via an insulation film on an area of said semiconductor substrate sandwiched between said source diffusion layer and said drain diffusion layer; and 
 control circuitry coupled to said memory cells to control operations of said memory cells, 
 wherein said control circuitry is constructed and performs control such that before writing data to selected memory cells in a subblock, every memory cell of the subblock is subjected to a write operation and then an erase operation, regardless of whether the memory cell is selected for writing data, 
 wherein the write operation is performed by injecting electrons into the charge storage film, the erase operation is performed by supplying holes from said gate electrode to said charge storage film, and electrons stored in said charge storage film and holes supplied from said gate electrode combine and disappear, and 
 wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell. 
 
     
     
       11. The semiconductor device according to  claim 10 , wherein the predetermined level is selected to be above a charge neutral threshold of the memory cell. 
     
     
       12. A semiconductor device comprising:
 memory cells each of which comprises: a first impurity doped region and a second impurity doped region formed on a main surface of a semiconductor substrate with a predetermined distance therebetween; and gate section that is formed by stacking a charge storage film and an electrode via an insulation film on an area of said semiconductor substrate sandwiched between said first impurity doped region and said second impurity doped region; and 
 control circuitry coupled to said memory cells to control operations of said memory cells, 
 wherein said control circuitry is constructed and performs control such that in an erase operation, holes are supplied from said electrode to said charge storage film, and electrons stored in said charge storage film and holes supplied from the electrode combine and disappear, and such that before data is written to selected memory cells of a predetermined group of memory cells, every memory cell of said group is subjected to a write operation and then an erase operation, regardless of whether the memory cell is selected for writing data, and 
 wherein each said memory cell is erased by reducing a threshold thereof, and the erase of the memory cell is stopped in response to a detection indicating that the threshold reaches a predetermined level selected to be above a threshold reduction saturation level of the memory cell. 
 
     
     
       13. The semiconductor device according to  claim 12 , wherein the predetermined level is selected to be above a charge neutral threshold of the memory cell. 
     
     
       14. The semiconductor device according to  claim 1 , wherein the predetermined level is selected to be above a charge neutral threshold of the memory cell. 
     
     
       15. The semiconductor device according to  claim 2 , wherein the predetermined level is selected to be above a charge neutral threshold of the memory cell. 
     
     
       16. The semiconductor device according to  claim 9 , wherein the predetermined level is selected to be above a charge neutral threshold of the memory cell. 
     
     
       17. The semiconductor device according to  claim 10 , wherein, in the case of the erase of a memory cell, a read current of the memory cell is detected and the erase is stopped in response to a detection that the read current reaches a predetermined value corresponding to said predetermined threshold level. 
     
     
       18. The semiconductor device according to  claim 12 , wherein, in the case of the erase of a memory cell, a read current of the memory cell is detected and the erase is stopped in response to a detection that the read current reaches a predetermined value corresponding to said predetermined threshold level.