Stacking package structure with chip embedded inside and die having through silicon via and method of the same

Abstract

The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.

1. A semiconductor device package structure, comprising:
 a first die with a through silicon via (TSV) open from a back side of said first die to expose bonding pads; 
 a build up layer coupled between said bonding pads to terminal metal pads by said TSV; 
 a substrate with a second die embedded inside and a top circuit wiring and a bottom circuit wiring on a top and a bottom side of said substrate respectively; 
 a conductive through hole structure coupled between said terminal metal pads to said top circuit wiring and said bottom circuit wiring; and 
 a top build up layer formed on said second die and said substrate, wherein said top build up layer includes a first dielectric layer, a redistribution layer (RDL), a via coupled to metal pads of said second die and said RDL, and a second dielectric layer on said first dielectric layer to cover said RDL. 
 
     
     
       2. The structure of  claim 1 , further comprising solder balls melted on said terminal metal pads, wherein said terminal pads are located under said substrate and/or said first die. 
     
     
       3. The structure of  claim 1 , wherein said build up layer includes a third dielectric layer and a fourth dielectric layer on said first dielectric layer. 
     
     
       4. The structure of  claim 1 , wherein the material of said substrate includes FR4, FR5, BT, PI and epoxy resin. 
     
     
       5. The structure of  claim 1 , further comprising an adhesion material encapsulated around said second die. 
     
     
       6. The structure of  claim 5 , wherein said adhesion material includes elastic material. 
     
     
       7. The structure of  claim 1 , wherein said first die includes an image sensor, an optic device, a memory device, a logic device, an analog device or a CPU device. 
     
     
       8. The structure of  claim 1 , wherein materials of said conductive through hole structure includes Cu, Cu/Ni or Sn/Ag/Cu. 
     
     
       9. The structure of  claim 1 , further comprising a second substrate under said substrate. 
     
     
       10. The structure of  claim 9 , wherein said second substrate with second top circuit wiring and second bottom circuit wiring on top and bottom side of said second substrate respectively. 
     
     
       11. A semiconductor device package structure, comprising:
 a first die with a through silicon via (TSV) open from a back side of said first die to expose bonding pads; 
 a build up layer coupled between said bonding pads to terminal metal pads by said TSV; 
 a substrate with a second die embedded inside and a top circuit wiring and a bottom circuit wiring on a top and a bottom side of said substrate respectively; 
 a conductive through hole structure coupled between said terminal metal pads to said top circuit wiring and said bottom circuit wiring; and 
 a bottom build up layer formed under said second die and said substrate, wherein said bottom build up layer includes a first dielectric layer, a redistribution layer (RDL), second terminal metal pads coupled to said RDL, and a second dielectric layer on said first dielectric layer to cover said RDL. 
 
     
     
       12. The structure of  claim 11 , further comprising solder balls melted on said terminal metal pads, wherein said terminal pads are located under said substrate and/or said first die. 
     
     
       13. The structure of  claim 11 , wherein said build up layer includes a third dielectric layer and a fourth dielectric layer on said first dielectric layer. 
     
     
       14. The structure of  claim 11 , wherein the material of said substrate includes FR4, FR5, BT, PI and epoxy resin. 
     
     
       15. The structure of  claim 11 , further comprising an adhesion material encapsulated around said second die. 
     
     
       16. The structure of  claim 15 , wherein said adhesion material includes elastic material. 
     
     
       17. The structure of  claim 11 , wherein said first die includes an image sensor, an optic device, a memory device, a logic device, an analog device or a CPU device. 
     
     
       18. The structure of  claim 11 , wherein materials of said conductive through hole structure includes Cu, Cu/Ni or Sn/Ag/Cu. 
     
     
       19. The structure of  claim 11 , further comprising a second substrate under said substrate. 
     
     
       20. The structure of  claim 19 , wherein said second substrate with second top circuit wiring and second bottom circuit wiring on top and bottom side of said second substrate respectively.