Scalable quantum well device and method for manufacturing the same

Abstract

A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

What is claimed is: 
     
       1. A method of manufacturing a quantum well device comprising:
 forming a quantum well region, comprising:
 forming a buffer structure by epitaxial growth, the buffer structure overlying the substrate and comprising a semiconductor material having a first band gap, 
 forming a channel structure by epitaxial growth, the channel structure overlying the buffer structure and comprising a semiconductor material having a second band gap, 
 forming a barrier layer by epitaxial growth, the barrier layer overlying the channel structure and comprising an un-doped semiconductor material having a third band gap, 
 wherein the first and the third band gap are wider than the second band gap, 
 
 forming a gate region overlying a portion of the quantum well region; and 
 forming a source region and a drain region self-aligned to the gate region by selective growth of a semiconductor material having a fourth band gap wider than the second band gap, 
 wherein each of the source region and the drain region comprises a doped region. 
 
     
     
       2. The method of  claim 1 , wherein forming the gate region comprises:
 forming a gate electrode overlying a portion of the barrier structure; and 
 forming a first pair of insulating sidewall spacers on both sides of the gate electrode. 
 
     
     
       3. The method of  claim 2 , further comprising forming a gate dielectric sandwiched in between the barrier layer and the gate electrode in the gate region. 
     
     
       4. The method of  claim 2 , wherein the width of each insulating sidewall spacer is less than or equal with about 5 nm. 
     
     
       5. The method of  claim 1 , further comprising, after forming the gate region, etching recesses on both sides of the gate region with a recess depth higher than the distance from the edge of the recess to the upper surface of the channel structure and lower than the distance from the edge of the recess to the bottom surface of buffer structure, so as to form recessed source and drains regions in the quantum well region. 
     
     
       6. The method of  claim 1 , wherein the doped region comprises a doping layer. 
     
     
       7. The method of  claim 1 , wherein the doped region is uniformly doped. 
     
     
       8. The method of  claim 1 , wherein the doped region is gradually doped, with the highest dopants concentration at the upper surface. 
     
     
       9. The method of  claim 1 , wherein the barrier layer has a thickness between about 3 Angstrom and 2 nm. 
     
     
       10. A quantum well device manufactured by the method of  claim 1 . 
     
     
       11. A method of manufacturing a n-type channel field effect transistor quantum well device, the method comprising:
 forming a quantum well region comprising:
 forming a buffer structure by epitaxial growth, the buffer structure overlying the substrate and comprising a III-V compound semiconductor material having a first band gap, 
 forming a channel structure by epitaxial growth, the channel structure overlying the buffer structure and comprising at a III-V compound semiconductor material having a second band gap, 
 forming a barrier layer by epitaxial growth, the barrier layer overlying the channel structure and comprising an un-doped III-V compound semiconductor material having a third band gap, 
 wherein the first and the third band gap are wider than the second band gap, 
 
 forming a gate region overlying a portion of the quantum well region; and 
 forming a source region and a drain region self-aligned to the gate region by selective growth of a III-V compound semiconductor material having a fourth band gap wider than the second band gap and wherein each of the source region and the drain region comprises a doped region. 
 
     
     
       12. A n-type channel field effect transistor quantum well device manufactured by the method of  claim 11 . 
     
     
       13. A method of forming a quantum well device, the method comprising:
 forming a buffer structure over a substrate, the buffer structure comprising a semiconductor material having a first band gap; 
 forming a channel structure over the buffer structure, the channel structure comprising a semiconductor material having a second band gap; 
 forming a barrier structure over the channel structure, the barrier structure comprising a semiconductor material having a third band gap and further comprising a doping material suitable for forming a 2-dimensional carrier gas; 
 forming a gate region over a portion of the barrier structure, the gate region comprising a gate electrode; 
 forming a source contact; and 
 forming a drain contact, 
 wherein the first and the third band gap are wider than the second band gap, and wherein no doping material is present in the portion of the barrier structure located underneath the gate region. 
 
     
     
       14. The method of  claim 13 , wherein forming the barrier structure comprises:
 forming a barrier layer over the channel structure, the barrier layer comprising an undoped semiconductor material having the third band gap, wherein the buffer structure, the channel structure, and the barrier layer together form a quantum well region; and 
 forming a source region and a drain region adjacent to the gate region, the source and drain regions being each self-aligned to the gate region and wherein the source and drain region comprise a semiconductor material having a fourth band gap and a doped region, wherein the fourth band gap is wider than the second band gap. 
 
     
     
       15. The method of  claim 14 , wherein the doped region comprises a doping layer. 
     
     
       16. The method of  claim 14 , wherein the doped region is uniformly doped. 
     
     
       17. The method of  claim 14 , wherein the doped region is gradually doped, with the highest dopants concentration at the upper surface. 
     
     
       18. The method of  claim 14 , further comprising a gate dielectric sandwiched in between the barrier layer and the gate electrode in the gate region. 
     
     
       19. The method of  claim 13 , wherein the gate electrode is over a portion of the barrier structure and a first pair of insulating sidewall spacers. 
     
     
       20. The method of  claim 19 , wherein the width of each insulating sidewall spacer is less than or equal with about 5 nm.