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US8192822B2ActiveUtilityPatentIndex 47

Edge etched silicon wafers

Assignee: ERK HENRY FPriority: Mar 31, 2008Filed: Mar 31, 2009Granted: Jun 5, 2012
Est. expiryMar 31, 2028(~1.7 yrs left)· nominal 20-yr term from priority
Inventors:ERK HENRY FALBRECHT PETER DHOLLANDER EUGENE RDOANE THOMAS ESCHMIDT JUDITH AVANDAMME ROLAND RZHANG GUOQIANG DAVID
H10P 90/126H10P 72/0426H10P 72/13H10P 50/644H10P 90/128Y10T428/21Y10T428/219
47
PatentIndex Score
1
Cited by
109
References
21
Claims

Abstract

The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Claims

exact text as granted — not AI-modified
1. A silicon wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a radius, R, extending from the central axis to a point along the peripheral edge, a point along the peripheral edge nearest the central axis, edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral point and the central axis and no more than about 15 mm from the nearest peripheral edge point, and central portions of the front and back surfaces of the wafer that extend from the point between the nearest peripheral point and the central axis and the central axis; wherein:
 the front and back surfaces of the wafer have a total thickness variation of at least 20 microns; 
 the central portions of the front and back surfaces of the wafer have a surface roughness of at least about 0.3 μm Ra; and 
 the edge portions of the front and back surfaces of the wafer have a surface roughness of less than about 0.3 μm Ra, the central portions of the front and back surfaces of the wafer having a surface roughness greater than the surface roughness of the edge portions of the front and back surface of the wafer. 
 
     
     
       2. The silicon wafer of  claim 1  wherein the front and back surfaces of the wafer have a total thickness variation of at least about 25 microns. 
     
     
       3. The silicon wafer of  claim 1  wherein the front and back surfaces of the wafer have a total thickness variation of at least about 35 microns. 
     
     
       4. The silicon wafer of  claim 1  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.3 to about 2.5 μm Ra. 
     
     
       5. The silicon wafer of  claim 1  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.7 to about 2 μm Ra. 
     
     
       6. The silicon wafer of  claim 1  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 1 to about 1.5 μm Ra. 
     
     
       7. The silicon wafer of  claim 1  wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.2 μm Ra. 
     
     
       8. The silicon wafer of  claim 1  wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.1 μm Ra. 
     
     
       9. The silicon wafer of  claim 1  wherein R is at least about 150 mm. 
     
     
       10. The silicon wafer of  claim 1  wherein the peripheral edge comprises two bevels and an apex. 
     
     
       11. The silicon wafer of  claim 1  wherein the peripheral edge is rounded. 
     
     
       12. A silicon wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a radius, R, extending from the central axis to a point along the peripheral edge, a point along the peripheral edge nearest the central axis, edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral point and the central axis, and central portions of the front and back surfaces of the wafer that extend from the point between the nearest peripheral point and the central axis and the central axis; wherein:
 the front and back surfaces of the wafer have a total thickness variation of at least 20 microns; 
 the central portions of the front and back surfaces of the wafer have a surface roughness of at least about 0.3 μm Ra; and 
 the edge portions of the front and back surfaces of the wafer have a surface roughness of less than about 0.2 μm Ra. 
 
     
     
       13. The silicon wafer of  claim 12  wherein the front and back surfaces of the wafer have a total thickness variation of at least about 25 microns. 
     
     
       14. The silicon wafer of  claim 12  wherein the front and back surfaces of the wafer have a total thickness variation of at least about 35 microns. 
     
     
       15. The silicon wafer of  claim 12  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.3 to about 2.5 μm Ra. 
     
     
       16. The silicon wafer of  claim 12  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.7 to about 2 μm Ra. 
     
     
       17. The silicon wafer of  claim 12  wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 1 to about 1.5 μm Ra. 
     
     
       18. The silicon wafer of  claim 12  wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.1 μm Ra. 
     
     
       19. The silicon wafer of  claim 12  wherein R is at least about 150 mm. 
     
     
       20. The silicon wafer of  claim 12  wherein the peripheral edge comprises two bevels and an apex. 
     
     
       21. The silicon wafer of  claim 12  wherein the peripheral edge is rounded.

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