Device having complex oxide nanodots

Abstract

Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric.

1. A device having a memory cell, the memory cell comprising:
 an active area formed of a semiconductor material; 
 a first dielectric over the semiconductor material; 
 a second dielectric comprising a material having a perovskite structure over the first dielectric, wherein the second dielectric comprises a plurality of spaced-apart nanodots, wherein the nanodots have a density in the range of about 1×10 11 /cm 2  to about 1×10 14 /cm 2 ; 
 a third dielectric over the second dielectric; and 
 a gate electrode over the third dielectric. 
 
     
     
       2. The device according to  claim 1 , wherein the second dielectric comprises a continuous layer of strontium titanate (STO). 
     
     
       3. The device according to  claim 1 , wherein the material of the second dielectric is selected from the group consisting of STO, BaTiO 3 , Pb(Mg 1/3 Nb 2/3 )O 3 , SrBi 2 Ta 2 O 9  and Ta 2 O 5 (Nb). 
     
     
       4. The device according to  claim 1 , wherein the nanodots and the semiconductor material have a band gap difference in the range of between about 2 eV and about 4 eV. 
     
     
       5. The device according to  claim 1 , wherein the second dielectric comprises STO nanodots. 
     
     
       6. The device according to  claim 5 , wherein a longest dimension of the STO nanodots are in a range of about 0.4 nm to about 100 nm. 
     
     
       7. The device according to  claim 5 , wherein at least some of the nanodots comprise Ti, Sr or O vacancies. 
     
     
       8. The device according to  claim 1 , wherein the memory cell is a flash memory cell. 
     
     
       9. A memory device comprising a transistor which comprises:
 a semiconductor layer; 
 a tunneling dielectric layer over the semiconductor layer; 
 a charge trapping layer over the tunneling dielectric layer, the charge trapping layer containing a plurality of localized charge storage sites embedded in the charge trapping layer, wherein the charge trapping layer includes spaced-apart nanodots, wherein the nanodots have a density in the range of about 1×10 11 /cm 2  to about 1×10 14 /cm 2 ; 
 a barrier dielectric layer over the charge trapping layer; and 
 a control gate over the barrier dielectric layer. 
 
     
     
       10. The device of  claim 9 , wherein the charge trapping layer has a perovskite structure. 
     
     
       11. The device of  claim 9 , wherein the charge trapping layer includes discrete, spaced-apart nanodots formed of complex oxides. 
     
     
       12. The device of  claim 11 , wherein the nanodots are formed of one or more materials selected from the group consisting of STO, BaTiO 3 , Pb(Mg 1/3 Nb 2/3 )O 3 , SrBi 2 Ta 2 O 9  and Ta 2 O 5 (Nb). 
     
     
       13. The device of  claim 11 , wherein the nanodots are in a range of about 0.4 nm to about 100 nm in each of their longest dimensions. 
     
     
       14. The device of  claim 11 , wherein the nanodots are formed of strontium titanate having a perovskite structure. 
     
     
       15. The device of  claim 11 , wherein the nanodots and the semiconductor layer have a band gap difference in the range of between about 2 eV and about 4 eV. 
     
     
       16. The device of  claim 11 , wherein at least some of the nanodots comprise Ti, Sr or O vacancies. 
     
     
       17. The device of  claim 9 , wherein the memory device is a non-volatile memory device. 
     
     
       18. The device of  claim 17 , wherein the memory device is a flash memory device. 
     
     
       19. The device of  claim 9 , wherein the transistor is a floating gate transistor.