US8310014B2ActiveUtilityA1

Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor

Assignee: SEO DAVIDPriority: Nov 23, 2009Filed: Oct 27, 2011Granted: Nov 13, 2012
Est. expiryNov 23, 2029(~3.3 yrs left)· nominal 20-yr term from priority
H10P 14/6332H10P 14/3406H10P 14/3206H10P 14/2901H10P 14/24H10P 14/22H10P 14/6902H10D 62/882H10D 30/6758H10D 30/6741H10D 30/6739H10D 30/675H10D 30/031
77
PatentIndex Score
3
Cited by
14
References
3
Claims

Abstract

Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10 −11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

Claims

exact text as granted — not AI-modified
1. A field effect transistor, comprising:
 a channel layer on a substrate; 
 a gate insulating layer on the channel layer, the gate insulating layer including both diamond-like carbon and tetrahedral amorphous carbon; 
 a gate electrode on the gate insulating layer; and 
 a source electrode and a drain electrode respectively on opposing sides of the channel layer so as to contact respective ends of the channel layer, 
 wherein the channel layer is one of a graphene layer and a Group III-V material layer. 
 
     
     
       2. The field effect transistor of  claim 1 , wherein upper surfaces of the source electrode and the drain electrode are on a same plane as an upper surface of the channel layer. 
     
     
       3. The field effect transistor of  claim 1 , wherein the source electrode and the drain electrode contact opposing sidewall of the gate insulating layer.

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