Multilayer printed wiring board

Abstract

A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

1. A multilayer printed wiring board comprising:
 a core substrate; 
 a built-up wiring layer having a first surface in contact with the core substrate and a second surface on an opposite side of the first surface, the second surface of the built-up wiring layer including a mounting area on which at least one semiconductor device is to be mounted, the built-up wiring layer comprising a plurality of conductor circuits and a plurality of insulating resin layers; 
 a plurality of first through-hole conductors formed in a first portion of the core substrate which corresponds to the mounting area of the second surface; 
 a plurality of second through-hole conductors formed in a second portion of the core substrate which corresponds to an area of the second surface other than the mounting area; 
 a plurality of third through-hole conductors formed in a processor core area of the first portion of the core substrate which corresponds to a processor core section of the at least one semiconductor device; and 
 a plurality of pads provided on the second surface, 
 wherein the first through-hole conductors have a pitch which is smaller than a pitch of the second through-hole conductors, and the third through-hole conductors have a pitch which is smaller than the pitch of the first through-hole conductors. 
 
     
     
       2. The multilayer printed wiring board of  claim 1 , wherein the pitch of the third through-hole conductors is 125-250 μm. 
     
     
       3. The multilayer printed wiring board of  claim 1 , wherein the pitch of the first through-hole conductors is 150-600 μm. 
     
     
       4. The multilayer printed wiring board of  claim 1 , wherein the pitch of the second through-hole conductors is 200-600 μm. 
     
     
       5. The multilayer printed wiring board of  claim 1 , wherein the pitch of the third through-hole conductors is matched to the pitch of the pads arranged directly below the processor core section of the semiconductor device. 
     
     
       6. The multilayer printed wiring board of  claim 1 , wherein the core substrate comprises a multilayer core substrate made by alternately layering conductor circuits and insulating resin layers on a core material, and when T represents a thickness of a conductor circuit formed inside the multilayer core substrate and t represents a thickness of a conductor circuit formed on an outer surface of the multilayer core substrate, T is greater than or equal to 1.5 t. 
     
     
       7. The multilayer printed wiring board of  claim 1 , wherein one of the first through-hole conductors is electrically connected to a base conductor layer of the multilayer printed wiring board and is positioned adjacent to one of the first through-hole conductors which is electrically connected to a power supply conductor layer of the multilayer printed wiring board. 
     
     
       8. The multilayer printed wiring board of  claim 7 , wherein one of the second through-hole conductors is electrically connected to a base conductor layer of the multilayer printed wiring board and is positioned adjacent to one of the second through-hole conductors which is electrically connected to a power supply conductor layer of the multilayer printed wiring board, such that a mutual inductance between adjacent through hole conductors in the first through hole conductors is less than a mutual inductance between adjacent through hole conductors in the second through hole conductors. 
     
     
       9. The multilayer printed wiring board of  claim 1 , wherein at least one of the plurality of first through-hole conductors and the plurality of second through-hole conductors does not include a dummy land. 
     
     
       10. A method of forming a multilayer printed wiring board comprising:
 providing a core substrate; 
 providing a built-up wiring layer on the core substrate, the built-up wiring layer having a first surface in contact with the core substrate and a second surface on an opposite side of the first surface, the second surface including a mounting area on which at least one semiconductor device is to be mounted, the built-up wiring layer comprising a plurality of conductor circuits and a plurality of insulating resin layers; 
 providing a plurality of first through-hole conductors in a first portion of the core substrate which corresponds to the mounting area of the second surface; 
 providing a plurality of second through-hole conductors in a second portion of the core substrate which corresponds to an area of the second surface other than the mounting area; 
 forming a plurality of third through-hole conductors in a processor core area of the first portion of the core substrate which corresponds to a processor core section of the at least one semiconductor device; and 
 forming a plurality of pads on the second surface, 
 wherein the first through-hole conductors have a pitch which is smaller than a pitch of the second through-hole conductors, and the third through-hole conductors have a pitch which is smaller than the pitch of the first through-hole conductors. 
 
     
     
       11. The method of  claim 10 , wherein the pitch of the third through-hole conductors is 125-250 μm, the pitch of the first through-hole conductors is 150-600 μm, and the pitch of the second through-hole conductors is 200-600 μm. 
     
     
       12. The method of  claim 10 , wherein the providing of the core substrate comprises providing a multilayer core substrate made by alternately layering conductor circuits and insulating resin layers on a core material, wherein when T represents a thickness of a conductor circuit formed inside the multilayer core substrate and t represents a thickness of a conductor circuit formed on an outer surface of the multilayer core substrate, T is greater than or equal to 1.5 t. 
     
     
       13. The method of  claim 10 , wherein at least one of the plurality of first through-hole conductors and the plurality of second through-hole conductors comprises a through-hole conductor that does not include a dummy land.