Integrated circuits using guard rings for ESD, systems, and methods for forming the integrated circuits

Abstract

An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

1. An integrated circuit comprising:
 at least one transistor over a substrate; 
 a first guard ring disposed around the at least one transistor, the first guard ring having a first type dopant; 
 a second guard ring disposed around the first guard ring, the second guard ring having a second type dopant; 
 a first doped region disposed adjacent to the first guard ring, the first doped region having the second type dopant; and 
 a second doped region disposed adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). 
 
     
     
       2. The integrated circuit of  claim 1  further comprising:
 a third guard ring disposed around the second guard ring, the third guard ring having the first type dopant; and 
 a third doped region disposed adjacent to the third guard ring, wherein the second guard ring, the third guard ring, the second doped region, and the third doped region are capable of being operable as a second silicon controlled rectifier (SCR) to substantially release the electrostatic discharge (ESD). 
 
     
     
       3. The integrated circuit of  claim 1 , wherein the at least one transistor comprises at least one diffused metal-gate-oxide (DMOS) transistor and the at least one DMOS transistor is capable of being operable if an operating voltage of the DMOS transistor is about 26 V or more. 
     
     
       4. The integrated circuit of  claim 3 , wherein the at least one DMOS transistor comprises a drain region, the drain region has the second type dopant, and the drain region is spaced from the first doped region by the first guard ring. 
     
     
       5. The integrated circuit of  claim 1 , wherein the SCR is capable of providing a human body model (HBM) of about 8 KV or more. 
     
     
       6. The integrated circuit of  claim 1 , wherein the first doped region is spaced from the second doped region by an isolation structure. 
     
     
       7. The integrated circuit of  claim 1  further comprising:
 a fourth doped region having the first type dopant, wherein the fourth doped region is disposed within the first guard ring and coupled with the second guard ring. 
 
     
     
       8. A system comprising:
 a converter; and 
 an integrated circuit coupled with the converter, the integrated circuit comprising:
 at least one transistor over a substrate; 
 a first guard ring disposed around the at least one transistor, the first guard ring having a first type dopant; 
 a second guard ring disposed around the first guard ring, the second guard ring having a second type dopant; 
 a first doped region disposed adjacent to the first guard ring, the first doped region having the second type dopant; and 
 a second doped region disposed adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). 
 
 
     
     
       9. The system of  claim 8 , wherein the integrated circuit further comprises:
 a third guard ring disposed around the second guard ring, the third guard ring having the first type dopant; and 
 a third doped region disposed adjacent to the third guard ring, wherein the second guard ring, the third guard ring, the second doped region, and the third doped region are capable of being operable as a second silicon controlled rectifier (SCR) to substantially release the electrostatic discharge (ESD). 
 
     
     
       10. The system of  claim 8 , wherein the at least one transistor comprises at least one diffused metal-gate-oxide (DMOS) transistor and the at least one DMOS transistor is capable of being operable if an operating voltage of the DMOS transistor is about 26 V or more. 
     
     
       11. The system of  claim 10 , wherein the at least one DMOS transistor comprises a drain region, the drain region has the second type dopant, and the drain region is spaced from the first doped region by the first guard ring. 
     
     
       12. The system of  claim 8 , wherein the SCR is capable of providing a human body model (HBM) of about 8 KV or more. 
     
     
       13. The system of  claim 8 , wherein the first doped region is spaced from the second doped region by an isolation structure. 
     
     
       14. An integrated circuit comprising:
 at least one transistor over a substrate; 
 a first guard ring disposed around the at least one transistor, the first guard ring comprising a first well having a first type dopant and a first pickup region having the first type dopant; 
 a second guard ring disposed around the first guard ring, the second guard ring comprising a second well having a second type dopant and a second pickup region having the second type dopant; and 
 a center well having the second type dopant, wherein a drain of the at least one transistor is formed in the center well and the first guard ring is disposed around the center well, wherein 
 the first pickup region is connected to a first voltage and the second pickup region is connected to a second voltage higher than the first voltage. 
 
     
     
       15. The integrated circuit of  claim 14 , further comprising a doped region formed around a source of the at least one transistor, the doped region having the first type dopant and configured to provide a channel for the at least one transistor. 
     
     
       16. The integrated circuit of  claim 15 , wherein the doped region is positioned between the first well and the first pickup region. 
     
     
       17. The integrated circuit of  claim 14 , further comprising a third guard ring disposed around the second guard ring, the third guard ring comprising a third well having the first type dopant and a third pickup region having the first type dopant, wherein the third pickup region is connected to the first voltage. 
     
     
       18. The integrated circuit of  claim 17 , wherein the third pickup region is separated from the second pickup region by an isolation structure. 
     
     
       19. The integrated circuit of  claim 14 , further comprising:
 an epitaxial layer having the first dopant type disposed on the substrate; and 
 a buried layer having the second dopant type disposed on the epitaxial layer, wherein the at least one transistor, the first guard ring and the second guard ring are disposed on the buried layer.