Methods of forming wiring structures

Abstract

A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.

What is claimed is: 
     
       1. A semiconductor memory wiring method comprising:
 receiving a substrate having a cell area and a peripheral circuit area; 
 depositing a first insulating layer on the substrate; 
 forming a first contact plug in the cell array region, the first contact plug comprising a first conductive material extending through the first insulating layer; 
 forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line comprising the first conductive material directly covering and integrated with the first contact plug; 
 forming a second contact plug in the peripheral circuit area at substantially the same time as forming the first contact plug, the second contact plug comprising the first conductive material extending through the first insulating layer; 
 forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line comprising the first conductive material directly covering and integrated with the second contact plug, and 
 simultaneously silicidating lateral portions along the first elongated conductive line and along the second elongated conductive line. 
 
     
     
       2. The method of  claim 1  wherein the first conductive line and the second conductive line are substantially parallel to each other. 
     
     
       3. The method of  claim 1  wherein the first insulating layer and the first and second contact plugs have upper surfaces disposed in substantially the same plane. 
     
     
       4. The method of  claim 1 , further comprising simultaneously silicidating the first contact plug, the first elongated conductive line, the second contact plug, and the second elongated conductive line. 
     
     
       5. The method of  claim 1 , further comprising forming at least one elongated trench in the substrate. 
     
     
       6. The method of  claim 5  wherein the at least one elongated trench is oriented parallel to the first elongated conductive line. 
     
     
       7. The method of  claim 5 , further comprising forming a gate electrode in the at least one trench disposed adjacent to the first contact plug. 
     
     
       8. The method of  claim 7 , further comprising: forming at least one third contact plug through the first insulating layer disposed on an opposite side of the gate electrode than the first contact plug, wherein the third contact plug extends higher than the first elongated conductive line. 
     
     
       9. The method of  claim 8 , further comprising forming a capacitor directly on the at least one third contact plug. 
     
     
       10. A semiconductor memory wiring method comprising:
 receiving a substrate; 
 depositing a first insulating layer on the substrate; 
 etching a first contact hole through the first insulating layer on an active region of the substrate; 
 simultaneously forming a first contact plug in the first contact hole and a conductive layer directly covering and integrated with the first contact plug, both of a first conductive material; 
 forming an elongated capping pattern along a first horizontal path on the conductive layer covering the first contact plug; 
 removing a portion of the conductive layer that extends outside of the elongated capping pattern to form a first elongated conductive line along the first horizontal path directly covering and integrated with the first contact plug; 
 forming an elongated photoresist pattern that extends along a second horizontal path substantially perpendicular to the first horizontal path, and 
 silicidating lateral portions along the first elongated conductive line. 
 
     
     
       11. The method of  claim 10  wherein the elongated photoresist pattern is disposed directly on the capping pattern. 
     
     
       12. The method of  claim 10  wherein upper boundaries of the first contact plug and the first insulating layer, and a lower boundary of the first elongated conductive line, are disposed in substantially the same horizontal plane. 
     
     
       13. The method of  claim 10 , further comprising simultaneously silicidating the first contact plug and the first elongated conductive line. 
     
     
       14. The method of  claim 10  wherein the first contact hole is disposed in a cell array region of the substrate, the method further comprising:
 etching a second contact hole through the first insulating layer in a peripheral circuit region of the substrate; and 
 simultaneously forming a second contact plug in the second contact hole and the conductive layer directly covering and integrated with the second contact plug, both of the first conductive material. 
 
     
     
       15. The method of  claim 10 , further comprising:
 forming at least one elongated trench in the substrate and oriented parallel to the first elongated conductive line; and 
 forming a gate electrode in the at least one trench disposed adjacent to the first contact plug. 
 
     
     
       16. The method of  claim 15 , further comprising:
 forming at least one third contact plug through the first insulating layer disposed on an opposite side of the gate electrode than the first contact plug, 
 wherein the third contact plug extends higher than the first elongated conductive line. 
 
     
     
       17. The method of  claim 16 , further comprising forming a capacitor directly on the at least one third contact plug.