Semiconductor device

Abstract

A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a semiconductor substrate having a first well region and a second well region; 
 a first gate electrode disposed on the first well region; 
 an N-type capping pattern and a first gate dielectric pattern disposed between the first well region and the first gate electrode; 
 a second gate electrode disposed on the second well region; and 
 a P-type capping pattern and a second gate dielectric pattern disposed between the second well region and the second gate electrode, wherein the first gate electrode and the second gate electrode are formed of a same material, 
 wherein the N-type capping pattern comprises at least one of LaO, GdO, DyO, SrO, BaO and ErO. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first gate dielectric pattern and the second gate dielectric pattern are formed of a same material. 
     
     
       3. The semiconductor device of  claim 1 , wherein the P-type capping pattern comprises an aluminum containing material. 
     
     
       4. The semiconductor device of  claim 3 , wherein the aluminum containing material comprises at least one of an aluminum oxide layer and an aluminum metal oxide layer. 
     
     
       5. The semiconductor device of  claim 2 , wherein the first gate dielectric pattern comprises at least one of a silicon oxide layer, a silicon oxide nitride layer, a hafnium oxide layer, a hafnium silicon oxide layer, a zirconium oxide layer, a zirconium silicon oxide layer, a hafnium oxide nitride layer, a hafnium silicon oxide nitride layer, a zirconium oxide nitride layer, a zirconium silicon oxide nitride layer, and a tantalum oxide layer. 
     
     
       6. The semiconductor device of  claim 2 , wherein the first gate dielectric pattern comprises a high-k dielectric material. 
     
     
       7. The semiconductor device of  claim 1 , wherein the first gate electrode comprises at least one of TaC, TaN, TaCN and TiN. 
     
     
       8. The semiconductor device of  claim 1 , wherein the first gate dielectric pattern comprises a first upper gate dielectric pattern and a first lower gate dielectric pattern. 
     
     
       9. The semiconductor device of  claim 1 , wherein the first well region comprises a P-type impurity region, and the second well region comprises an N-type impurity region. 
     
     
       10. The semiconductor device of  claim 1 , wherein the semiconductor substrate comprises a semiconductor fin protruding therefrom, the first well region is disposed in the semiconductor fin, and the first gate electrode crosses the first well region. 
     
     
       11. The semiconductor device of  claim 1 , further comprising another P-type capping pattern disposed between the first well region and the first gate electrode. 
     
     
       12. The semiconductor device of  claim 8 , wherein the N-type capping pattern is disposed between the first upper gate dielectric pattern and the first lower gate dielectric pattern. 
     
     
       13. The semiconductor device of  claim 8 , wherein the N-type capping pattern is disposed on the first upper gate dielectric pattern. 
     
     
       14. The semiconductor device of  claim 13 , wherein the N-type capping pattern is disposed directly on the first upper gate dielectric pattern. 
     
     
       15. The semiconductor device of  claim 11 , wherein the first gate dielectric pattern is disposed between the N-type capping pattern and the another P-type capping pattern. 
     
     
       16. The semiconductor device of  claim 1 , further comprising a device isolation layer disposed between the first well region and the second well region. 
     
     
       17. The semiconductor device of  claim 8 , wherein the first upper gate dielectric pattern comprises at least one of a silicon oxide layer, a silicon oxide nitride layer, a hafnium oxide layer, a hafnium silicon oxide layer, a zirconium oxide layer, a zirconium silicon oxide layer, a hafnium oxide nitride layer, a hafnium silicon oxide nitride layer, a zirconium oxide nitride layer, a zirconium silicon oxide nitride layer, and a tantalum oxide layer, and the first lower gate dielectric pattern comprises at least one of a silicon oxide layer, a silicon oxide nitride layer, and a high-k dielectric layer. 
     
     
       18. A semiconductor device, comprising:
 a semiconductor substrate having a first well region and a second well region; 
 a first gate electrode disposed on the first well region; 
 an N-type capping pattern and a first gate dielectric pattern disposed between the first well region and the first gate electrode; 
 a second gate electrode disposed on the second well region; and 
 a P-type capping pattern and a second gate dielectric pattern disposed between the second well region and the second gate electrode, wherein the first gate electrode and the second gate electrode are formed of a same material, 
 wherein the P-type capping pattern comprises an aluminum containing material. 
 
     
     
       19. A semiconductor device, comprising:
 a semiconductor substrate having a first well region and a second well region; 
 a first gate electrode disposed on the first well region; 
 an N-type capping pattern and a first gate dielectric pattern disposed between the first well region and the first gate electrode; 
 a second gate electrode disposed on the second well region; 
 a P-type capping pattern and a second gate dielectric pattern disposed between the second well region and the second gate electrode, wherein the first gate electrode and the second gate electrode are formed of a same material; and 
 another P-type capping pattern disposed between the first well region and the first gate electrode. 
 
     
     
       20. The semiconductor device of  claim 19 , wherein the first gate dielectric pattern is disposed between the N-type capping pattern and the other P-type capping pattern.