Metal-free integrated circuits comprising graphene and carbon nanotubes
Abstract
An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, the method comprising:
forming a graphene layer on a substrate;
doping a portion of the graphene layer, resulting in a region of doped graphene adjacent a region of undoped graphene;
forming a dielectric layer on top of the graphene layer;
a via formed through the dielectric layer;
forming a carbon nanotube film in the via and over the region of undoped graphene;
etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene, the gate comprising a first portion of the etched carbon nanotube film that is isolated from the undoped graphene channel by the dielectric layer; and
wherein etching the carbon nanotube film also forms a top level interconnect on top of the dielectric layer and in contact with the via, the top level interconnect comprising a second portion of the etched carbon nanotube film that is separated from the first portion of the etched carbon nanotube film.
2. The method of claim 1 , wherein the dielectric layer comprises an oxide material.
3. The method of claim 1 , wherein the graphene layer is between about 0.35 nanometers (nm) and about 7 nm thick.
4. The method of claim 1 , wherein the substrate comprises an oxide material.
5. The method of claim 1 , further comprising patterning the graphene layer by etching, and doping the etched graphene layer with an organic molecule.
6. The method of claim 5 , wherein the organic molecule comprises polyethylemneimine.
7. The method of claim 5 , wherein the organic molecule comprises diazonium.Cited by (0)
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