P
US9054018B2ActiveUtilityPatentIndex 72

Semiconductor device and method for manufacturing the same

Assignee: MA XIAOLONGPriority: Aug 16, 2012Filed: Oct 12, 2012Granted: Jun 9, 2015
Est. expiryAug 16, 2032(~6.1 yrs left)· nominal 20-yr term from priority
Inventors:MA XIAOLONGYIN HUAXIANGXU SENZHU HUILONG
H10D 64/691H10D 62/8161H10D 62/822H10D 30/6212H10D 30/751H10D 30/472H10D 30/62H10D 30/024H10D 30/015H10D 62/235H10D 62/815H01L 29/517H01L 29/151H01L 29/66795B82Y 10/00H01L 29/785H01L 29/1054H01L 29/15H01L 29/165H01L 29/7853
72
PatentIndex Score
5
Cited by
9
References
14
Claims

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device, comprising:
 a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections, and wherein each fin is consisting of one semiconductor material; 
 a gate stack structure that traverses each fin and extends along a second direction; 
 a channel region located under the gate stack structure in each fin; and 
 source and drain regions located at both sides of the gate stack structure in each fin; 
 a quantum well layer is disposed between the fins and the gate stack structure; and 
 wherein, the quantum well layer comprises a SiGe alloy. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein, the gate stack structure comprises a gate insulating layer of a high-K material and a gate conductive layer of a metal material. 
     
     
       3. The semiconductor device according to  claim 1 , wherein, there are raised source and drain regions at both sides of the gate stack structure on each fin. 
     
     
       4. The semiconductor device according to  claim 1 , wherein, the substrate is SOI and the fins include Si. 
     
     
       5. A method for manufacturing a semiconductor device, comprising:
 forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections sections, and wherein each cross-section is consisting of one semiconductor material; 
 forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; 
 wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions; 
 wherein the step of forming a plurality of fins further comprises: 
 forming a plurality of fins on the substrate, which extend along a first direction and have rectangular cross-sections; 
 forming an epitaxial layer on each fin; and 
 etching the epitaxial layer and the fins to form fins having rhombus-like cross-sections. 
 
     
     
       6. The method for manufacturing a semiconductor device according to  claim 5 , wherein, the fins are etched by KOH or TMAH wet etching. 
     
     
       7. The method for manufacturing a semiconductor device according to  claim 5 , wherein, the width at the middle of the fin having a rhombus-like cross-section is greater than the width at the bottom thereof, and the top thereof is a sharp angle. 
     
     
       8. The method for manufacturing a semiconductor device according to  claim 5 , wherein, after forming fins having rhombus-like cross-sections and before forming the gate stack structure, the method further comprises forming a quantum well layer on the fins. 
     
     
       9. The method for manufacturing a semiconductor device according to  claim 8 , wherein, the quantum well layer comprises a SiGe alloy. 
     
     
       10. The method for manufacturing a semiconductor device according to  claim 5 , wherein, the gate stack structure comprises a gate insulating layer of a high-K material and a gate conductive layer of a metal material. 
     
     
       11. The method for manufacturing a semiconductor device according to  claim 5 , wherein, after forming the gate stack structure, the method further comprises forming gate spacers and raised source and drain regions at both sides of the gate stack structure. 
     
     
       12. The method for manufacturing a semiconductor device according to  claim 5 , wherein, the substrate is SOI and the fins include Si. 
     
     
       13. The method for manufacturing a semiconductor device according to  claim 5 , wherein, after forming the fins having rhombus-like cross-sections, the corners of the fins are further smoothed by an isotropic wet or dry etching method. 
     
     
       14. The method for manufacturing a semiconductor device according to  claim 5 , wherein, the width at the middle of the fin having a rhombus-like cross-section is greater than the width at the bottom thereof, and the top thereof is a sharp angle.

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