Method of depositing a diffusion barrier for copper interconnect applications

Abstract

The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

What is claimed is: 
     
       1. A method for depositing a metal-containing material on a substrate, the method comprising:
 (a) receiving a wafer substrate comprising at least one via comprising a bottom portion, at least one trench having a horizontal surface, and a field, wherein the substrate comprises an exposed metal at the bottom portion of the at least one via; 
 (b) depositing a first portion of the metal-containing material at least over the bottom portion of the at least one via using a metal from a deposition source; 
 (c) etching away the first portion of the metal-containing material at the bottom of the at least one via, such that an E/D (etch rate to deposition rate) ratio is greater than 1 at the bottom of the at least one via, with energetic inert gas ions without fully etching through to partially remove the first portion of the metal-containing material such that a part of the first portion of the metal-containing material remains at the bottom of the at least one via and a part of the first portion of the metal-containing material is removed from the bottom portion of the at least one via, such that the resistance of subsequently formed interconnects is reduced relative to that of interconnects formed using the first portion of the metal-containing material prior to etching, while simultaneously depositing a second portion of the metal-containing material in the trench and/or field on the wafer substrate, comprising a PVD etch/deposition process in which the wafer substrate is biased with an RF frequency source such that the etch rate at the bottom of the at least one via is greater than an etch rate on any associated horizontal trench surfaces or the field. 
 
     
     
       2. The method of  claim 1 , wherein the RF frequency is between about 100 kHz and 50 MHz. 
     
     
       3. The method of  claim 1 , further comprising using a source power of between about 1 and 10 kW. 
     
     
       4. The method of  claim 3 , further comprising using an RF power of about 350 W. 
     
     
       5. The method of  claim 4 , further comprising using an Ar flow of about 10 to 300 SCCM. 
     
     
       6. The method of  claim 5 , further comprising using a pressure of 0.1-100 mTorr. 
     
     
       7. The method of  claim 5 , further comprising using a pressure of about 8 mTorr.