Semiconductor device having metal gate and manufacturing method thereof

Abstract

A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

What is claimed is: 
     
       1. A semiconductor device having metal gate comprising:
 a substrate; 
 a first metal gate positioned on the substrate, the first metal gate comprising a first P-work function metal layer, an N-work function metal layer, and a gap-filling metal layer; and 
 a second metal gate positioned on the substrate, the second metal gate comprising a second P-work function metal layer, the N-work function metal layer, and the gap-filling metal layer, wherein 
 the first P-work function metal layer and the second P-work function metal layer comprise a same metal material and a same metal concentration, a thickness of the first P-work function metal layer is larger than a thickness of the second P-work function metal layer, and the first P-work function metal layer, the second P-work function metal layer, and the N-work function metal layer comprise a U shape. 
 
     
     
       2. The semiconductor device having metal gate according to  claim 1 , further comprising a high-k gate dielectric layer formed in between the first metal gate and the substrate, and between the second metal gate and the substrate. 
     
     
       3. The semiconductor device having metal gate according to  claim 2 , wherein the high-k gate dielectric layer comprises a U shape. 
     
     
       4. The semiconductor device having metal gate according to  claim 2 , wherein the high-k gate dielectric layer comprises a flat shape. 
     
     
       5. The semiconductor device having metal gate according to  claim 2 , further comprises an interfacial layer positioned between the high-k gate dielectric layer and the substrate.