FinFETs with vertical fins and methods for forming the same

Abstract

In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.

What is claimed is: 
     
       1. A device comprising:
 a (100) silicon substrate; 
 a planar oxide layer on a top surface of the (100) silicon substrate; 
 insulation regions over and contacting the planar oxide layer, wherein interfaces between the insulation regions and the planar oxide layer are distinguishable, and are substantially planar; and 
 a semiconductor strip extending from a top surface of the insulation regions into the insulation regions and the planar oxide layer, wherein a bottom surface of the semiconductor strip contacts the (100) silicon substrate, wherein the semiconductor strip has a lattice constant equal to a lattice constant of the (100) silicon substrate. 
 
     
     
       2. The device of  claim 1 , wherein the semiconductor strip is in physical contact with two of the insulation regions on opposite sides of the semiconductor strip. 
     
     
       3. The device of  claim 1 , wherein a top portion of the semiconductor strip is over the top surface of the insulation regions to form a semiconductor fin, and the device further comprises:
 a gate dielectric on sidewalls of the semiconductor fin, wherein the gate dielectric is in physical contact with a top surface of the insulation regions; and 
 a gate electrode over the gate dielectric. 
 
     
     
       4. The device of  claim 1 , wherein the planar oxide layer and the insulation regions are formed of essentially a same compound dielectric material, and wherein the planar oxide layer and the insulation regions have distinguishable interfaces. 
     
     
       5. The device of  claim 1 , wherein the planar oxide layer and the insulation regions comprise different materials. 
     
     
       6. The device of  claim 1 , wherein the planar oxide layer has a thickness between about 1 Å and about 500 Å. 
     
     
       7. The device of  claim 1 , wherein the semiconductor strip has a (100) top surface orientation. 
     
     
       8. The device of  claim 1 , wherein a bottom surface of the semiconductor strip is substantially level with a bottom surface of the planar oxide layer. 
     
     
       9. The device of  claim 1 , wherein the semiconductor strip comprises crystalline silicon. 
     
     
       10. A device comprising:
 a (100) silicon substrate; 
 an oxide layer over a top surface of the (100) silicon substrate; 
 a first semiconductor strip and a second semiconductor strip over and contacting the top surface of the (100) silicon substrate, wherein the first semiconductor strip and the second semiconductor strip penetrate through, and are in contact with, the oxide layer, wherein the first semiconductor strip and the second semiconductor strip are silicon strips free from germanium and III-V compound semiconductors; and 
 an insulation region over and contacting the oxide layer, wherein interfaces between the insulation region and the oxide layer are distinguishable, and wherein the insulation region is between, and in contact with, sidewalls of the first semiconductor strip and the second semiconductor strip. 
 
     
     
       11. The device of  claim 10 , wherein the semiconductor strip has a lattice constant equal to a lattice constant of the (100) silicon substrate. 
     
     
       12. The device of  claim 10 , wherein an interface between the insulation region and the oxide layer is substantially planar. 
     
     
       13. The device of  claim 10 , wherein edges of the oxide layer are in contact with the sidewalls of the first semiconductor strip and the second semiconductor strip. 
     
     
       14. The device of  claim 10 , wherein bottom surfaces of the first semiconductor strip and the second semiconductor strip are substantially level with a bottom surface of the oxide layer. 
     
     
       15. The device of  claim 10 , wherein the first semiconductor strip and the second semiconductor strip further extend over top surfaces of the insulation regions to form semiconductor fins, and the device comprises:
 a gate dielectric on sidewalls of the semiconductor fins, wherein the gate dielectric is in physical contact with a top surface of the insulation region; and 
 a gate electrode over the gate dielectric. 
 
     
     
       16. A device comprising:
 a (100) silicon substrate; 
 an oxide layer over a top surface of the (100) silicon substrate; 
 a first semiconductor strip and a second semiconductor strip over and contacting the top surface of the (100) silicon substrate, wherein the first semiconductor strip and the second semiconductor strip have (100) top surfaces; and 
 an insulation region over and contacting the oxide layer, wherein the insulation region and the oxide layer are formed of a same compound dielectric material, with a distinguishable interface between the oxide layer and the insulation region, and wherein the insulation region is between, and in contact with, sidewalls of the first semiconductor strip and the second semiconductor strip. 
 
     
     
       17. The device of  claim 16 , wherein the first and the second semiconductor strips have a lattice constant equal to a lattice constant of the (100) silicon substrate. 
     
     
       18. The device of  claim 16 , wherein edges of the oxide layer are in contact with the sidewalls of the first semiconductor strip and the second semiconductor strip. 
     
     
       19. The device of  claim 16 , wherein bottom surfaces of the first semiconductor strip and the second semiconductor strip are substantially level with a bottom surface of the oxide layer. 
     
     
       20. The device of  claim 16 , wherein the first semiconductor strip further extends over top surfaces of the insulation regions to form a semiconductor fin, and the device further comprises:
 a gate dielectric on sidewalls of the semiconductor fin, wherein the gate dielectric is in physical contact with a top surface of the insulation region; and 
 a gate electrode over the gate dielectric.