P
US9202767B2ActiveUtilityPatentIndex 56

Semiconductor device and method of manufacturing the same

Assignee: KIM JI HWANGPriority: Mar 8, 2011Filed: Mar 16, 2012Granted: Dec 1, 2015
Est. expiryMar 8, 2031(~4.7 yrs left)· nominal 20-yr term from priority
Inventors:KIM JI-HWANGCHOI KWANG-CHULKIM SANGWONMIN TAE-HONG
H10W 99/00H10W 90/734H10W 90/732H10W 90/724H10W 90/722H10W 90/701H10W 90/297H10W 90/288H10W 90/28H10W 74/147H10W 74/142H10W 74/129H10W 74/121H10W 74/15H10W 74/012H10W 72/9415H10W 72/952H10W 72/942H10W 72/934H10W 72/923H10W 72/922H10W 72/877H10W 72/252H10W 72/242H10W 72/072H10W 72/29H10W 72/00H10W 70/698H10W 70/655H10W 42/20H10W 20/49H10W 90/00H10W 20/023H10W 20/20H10W 20/0245H10W 20/0249H10W 40/10H01L 21/563H01L 2225/06513H01L 2924/00H01L 2225/06517H01L 23/48H01L 23/525H01L 23/481H01L 25/0657H01L 23/3135H01L 2224/02379H01L 24/81H01L 2224/73204H01L 2224/05552H01L 2224/32145H01L 2224/05556H01L 23/3114H01L 2224/0401H01L 2224/16145H01L 2224/05548H01L 2224/16227H01L 2224/16225H01L 2224/73253H01L 23/49816H01L 2224/0519H01L 2224/13021H01L 2224/13022H01L 2224/32225H01L 2224/0557H01L 23/147H01L 2224/131H01L 24/73H01L 23/36H01L 24/80H01L 23/552H01L 2924/18161H01L 2924/15311H01L 21/76898H01L 2924/00014H01L 24/32H01L 2924/014H01L 2225/06568H01L 2225/06589H01L 23/3192H01L 24/16H01L 2225/06544H01L 24/13
56
PatentIndex Score
2
Cited by
13
References
15
Claims

Abstract

Provided are a semiconductor device including a through via plug and a method of manufacturing the same. In the semiconductor device, since a redistributed interconnection pattern is disposed on a protection film of a convex-concave structure having a protrusion and a recessed portion, the semiconductor device may have improved reliability while preventing a leakage current. In the method of manufacturing the semiconductor device, since an end surface of through via structure is exposed by removing a protection film and an insulating film liner using a selective etching process, damage to the through via structure is minimized, thereby preventing copper contamination in a substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate including a first surface and a second surface; 
 a protection film having a protrusion and a recessed portion, the protection film being disposed on the first surface; 
 a through via structure penetrating the substrate and the protection film and including an end surface coplanar with or higher than the recessed portion of the protection film; 
 a first interconnection pattern conformally covering a side surface and a lower surface of the recessed portion of the protection film, wherein a surface of the first interconnection pattern is coplanar with a surface of the protrusion; 
 a second interconnection pattern covering the first interconnection pattern and disposed in the recessed portion of the protection film, wherein a top surface of the first interconnection pattern is exposed by the second interconnection pattern; and 
 a mask pattern having an etching selectivity with respect to the protection film, the mask pattern being interposed between the protection film and the second interconnection pattern. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the protrusion of the protection film is higher than the end surface of the through via structure. 
     
     
       3. The semiconductor device of  claim 1 , wherein the through via structure comprises:
 a through via plug; 
 a through via seed film on a side surface of the through via plug; and 
 a diffusion prevention film on a side surface of the through via seed film and at the end surface of the through via structure. 
 
     
     
       4. The semiconductor device of  claim 1 , further comprising an insulating film liner between the through via structure and the substrate and between the through via structure and the protection film, wherein an angle between a top surface of the insulating film liner and a side surface of the through via structure is 90 degree or less. 
     
     
       5. The semiconductor device of  claim 1 , wherein the insulating film liner and the protection film include a same material. 
     
     
       6. The semiconductor device of  claim 1 , wherein a width of the recessed portion is greater than a width of the through via structure. 
     
     
       7. The semiconductor device of  claim 1 , further comprising interconnections and an interlayer insulating film on the second surface. 
     
     
       8. A semiconductor device comprising:
 a substrate having a first surface and a second surface; 
 a protection film on the first surface of the substrate, wherein the protection film includes at least one portion recessed toward the second surface of the substrate; 
 a through via structure formed through the substrate and the recessed portion of the protection film in a direction perpendicular to the substrate and the protection film; 
 a first interconnection pattern covering a side surface and a lower surface of the recessed portion of the protection film and an end surface of the through via structure, wherein an upper surface of the first interconnection pattern on the through via structure is disposed at a higher level than the upper surface of the first interconnection pattern on the lower surface of the recessed portion of the protection film; and 
 a second interconnection pattern formed on the first interconnection pattern. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein a top surface of the through via structure is coplanar with a top surface of the recessed portion of the protection film. 
     
     
       10. The semiconductor device of  claim 8 , wherein a top surface of the through via structure is higher than a top surface of the recessed portion of the protection film. 
     
     
       11. The semiconductor device of  claim 8 , wherein the through via structure comprises:
 a through via plug; 
 a through via seed film covering the through via plug; and 
 a diffusion prevention film covering the through via seed film. 
 
     
     
       12. The semiconductor device of  claim 8 , further comprising an insulating film liner between the through via structure and the substrate and between the through via structure and the protection film, wherein a top surface of the insulating film liner is coplanar with a top surface of the recessed portion of the protection film. 
     
     
       13. The semiconductor device of  claim 8 , further comprising an insulating film liner between the through via structure and the substrate and between the through via structure and the protection film, wherein a top surface of the insulating film liner is inclined toward a side surface of the through via structure. 
     
     
       14. The semiconductor device of  claim 8 , further comprising:
 a mask pattern on a top surface of the protection film except for the recessed portion; 
 a first auxiliary interconnection pattern on the first and second interconnection patterns and part of the mask pattern; and 
 a second auxiliary interconnection pattern on the first auxiliary interconnection pattern, wherein top surfaces of the first and second interconnection patterns are coplanar with a top surface of the part of the mask pattern. 
 
     
     
       15. A semiconductor device comprising:
 a substrate having a first surface and a second surface; 
 a protection film on the first surface of the substrate, wherein the protection film includes at least one portion recessed toward the second surface of the substrate; 
 a through via structure formed through the substrate and the recessed portion of the protection film in a direction perpendicular to the substrate and the protection film; 
 a first interconnection pattern covering a side surface and a lower surface of the recessed portion of the protection film; and 
 a second interconnection pattern covering the first interconnection pattern and disposed in the recessed portion of the protection film, wherein an upper surface of the second interconnection pattern is substantially coplanar with an uppermost surface of the first interconnection pattern.

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