Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

Abstract

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

We claim:  
     
       1. A method of forming a semiconductor device comprising:
 opening trenches in the semiconductor substrate and filling each of the trenches with a gate electrode followed by etching the gate electrode back to form a recessed gate electrode thus leaving a semiconductor protuberance between two adjacent trenches; 
 implanting a body dopant of a first conductivity type to form a body region in an upper portion of the semiconductor protuberance followed by implanting a source dopant of a second conductivity type to form source region encompassed in the body region; 
 filling a recessed top portion of the trenches with an insulation plug followed by removing a top portion of the insulation plug to a top surface level of the semiconductor protuberances and selectively etching and removing a top portion of the semiconductor protuberances to form a recessed protuberance top surface below the insulation plug and above the gate electrode and exposing the source region and the body region immediately below the protuberance top surface; and 
 forming a silicide layer covering substantially over an entire area of the recessed protuberance top surface to directly contacting the source region and the body region. 
 
     
     
       2. The method of  claim 1  wherein:
 the step of a filling the trenches with a gate electrode further comprising a step of forming in each of the trenches with a shield electrode in a lower portion of the trenches and forming an inter-electrode-dielectric separating the shield and gate electrodes from an upper gate electrode whereby forming the device as a shield gate trench power device. 
 
     
     
       3. The method of  claim 1  wherein
 the step of etching the gate electrode back to form a recessed gate electrode further comprising a step of forming on top of the recessed gate electrode a silicide layer. 
 
     
     
       4. The method of  claim 1  wherein:
 the step of forming a silicide layer covering substantially over an entire area of the recessed protuberance top surface further comprising a step of forming the silicide layer with one metal from a group of metals consisted of titanium, tungsten, nickel, cobalt, or palladium. 
 
     
     
       5. The method of  claim 1  wherein:
 the step of forming a silicide layer covering substantially over an entire area of the recessed protuberance top surface further comprising a step of forming the silicide layer to laterally extend over the protuberance top surface to reach the sidewalls of the gate trenches. 
 
     
     
       6. The method of  claim 1  wherein
 the step of opening a plurality of trenches in the semiconductor substrate further comprising a step of opening a wide trench in a terminal area of having a greater width than the trenches in an active area. 
 
     
     
       7. The method of  claim 6  wherein:
 the step of a filling the trenches with a gate electrode further comprising a step of forming a shield electrode in a lower portion of the wide trench followed by forming an inter-layer-dielectric (ILD) layer separating and shielding the shield electrode in the wide trench from an upper gate electrode. 
 
     
     
       8. The method of  claim 7  further comprising:
 forming a shield electrode contact in the wide trench with a conductive shield electrode contact penetrating through the ILD layer in a middle portion of the wide trench and extends downward for contacting the bottom shield electrode. 
 
     
     
       9. The method of  claim 8  further comprising:
 forming a source metal covering over the wide trench in the terminal area and to contact the shield electrode contact whereby the source metal is electrically connected to the bottom shielded electrodes. 
 
     
     
       10. The method of  claim 6  wherein
 the step of a filling the trenches with a gate electrode further comprising a step of forming the recessed electrode in the wide trench to electrically connect to at least another one of the recessed gate electrodes. 
 
     
     
       11. The method of  claim 1  further comprising
 forming a top insulation layer for covering over the top surface of the semiconductor device and opening a trenched source/body contact penetrates through the top insulation for contacting the silicide layer disposed on the protuberance top surface. 
 
     
     
       12. The method of  claim 1  wherein
 the step of forming the source regions further comprising a step of forming the source regions having a width ranging between 0.05 to 0.2 microns. 
 
     
     
       13. The method of  claim 1  wherein
 the step of opening a plurality of trenches in the semiconductor substrate further comprising a step of opening a trench in a terminal area of having a greater width and a greater depth than the trenches in an active area.