Integrated circuit heat dissipation using nanostructures

Abstract

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

What is claimed: 
     
       1. A method of manufacturing a semiconductor structure, comprising:
 forming an isolation layer on an electrically conductive feature of an integrated circuit device, wherein the isolation layer is electrically insulating and thermally conducting; 
 forming an electrically conductive layer on the isolation layer; and 
 forming a plurality of nanowire structures on a surface of the electrically conductive layer, 
 wherein the forming the plurality of nanowire structures comprises growing a plurality of spaced apart columnar structures each having a sub-micron width, 
 wherein the growing comprises:
 submerging at least the electrically conductive layer in a growth solution comprising a zinc source; and 
 applying an electric potential between a first electrode wired to the electrically conductive layer and a second electrode submerged in the growth solution, and 
 
 further comprising forming a discontinuity in a wiring path that electrically connects a contact pad to the electrically conductive layer. 
 
     
     
       2. The method of  claim 1 , wherein the forming the isolation layer comprises forming a high thermal conductivity material that electrically isolates the electrically conductive feature from the electrically conductive layer. 
     
     
       3. The method of  claim 1 , wherein the isolation layer comprises polymorphic ceramic. 
     
     
       4. The method of  claim 1 , wherein the isolation layer comprises one of alumina (Al 2 O 3 ), boron nitride (BN), zirconia (ZrO 2 ), and aluminum nitride (AlN). 
     
     
       5. The method of  claim 1 , wherein the electrically conductive feature is a heat-producing device and comprises at least one of: a resistor; a base of a bipolar junction transistor; and a source region or a drain region of a field effect transistor. 
     
     
       6. The method of  claim 1 , wherein the forming the electrically conductive layer comprises forming silicide on the isolation layer. 
     
     
       7. A semiconductor structure, comprising:
 an isolation layer on an electrically conductive feature of an integrated circuit device; 
 an electrically conductive layer on the isolation layer; 
 a plurality of nanowire structures on a surface of the electrically conductive layer; 
 a wiring path that electrically connects the electrically conductive layer to a contact pad that is structured and arranged to contact an electrode during an electrochemical deposition process; and 
 an e-fuse in the wiring path that is structured and arranged to create a discontinuity in the wiring path when blown with a programming voltage, 
 wherein the isolation layer electrically isolates the electrically conductive feature from the electrically conductive layer, and 
 the plurality of nanowire structures are composed of a high thermal conductivity material that provides a heat path away from the electrically conductive feature. 
 
     
     
       8. The structure of  claim 7 , wherein the electrically conductive feature comprises a resistor. 
     
     
       9. The structure of  claim 7 , wherein the electrically conductive feature comprises a base of a bipolar junction transistor. 
     
     
       10. The structure of  claim 7 , wherein the electrically conductive feature comprises a source region or a drain region of a field effect transistor. 
     
     
       11. The structure of  claim 7 , wherein:
 the isolation layer comprises Al 2 O 3 ; 
 the electrically conductive layer comprises silicide; and 
 the plurality of nanowire structures comprises a plurality of spaced apart ZnO columnar structures each having a sub-micron width. 
 
     
     
       12. A semiconductor structure, comprising:
 an isolation layer on an electrically conductive feature of an integrated circuit device; 
 an electrically conductive layer on the isolation layer; and 
 a plurality of nanowire structures on a surface of the electrically conductive layer, 
 wherein the isolation layer electrically isolates the electrically conductive feature from the electrically conductive layer, and 
 the plurality of nanowire structures are composed of a high thermal conductivity material that provides a heat path away from the electrically conductive feature, 
 the electrically conductive feature comprises a first portion of a drain region of a field effect transistor, and further comprising: 
 a second plurality of nanowire structures on a first portion of a source region of the field effect transistor, wherein the second plurality of nanowire structures are composed of the high thermal conductivity material; 
 a plurality of drain contacts on a second portion of the drain region; and 
 a plurality of source contacts on a second portion of the source region.