Multiple-time programming memory cells and methods for forming the same

Abstract

A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

What is claimed is: 
     
       1. A method comprising:
 etching a portion of a Shallow Trench Isolation (STI) region to form a recess, with a sidewall of a first active region of a semiconductor substrate exposed to the recess, wherein the STI region further comprises a lower portion overlapped by the etched portion of the STI region; 
 implanting a side surface layer of the first active region to form an implantation region, wherein the side surface layer is exposed to the recess; 
 oxidizing an outer portion of the side surface layer to form a capacitor insulator of a capacitor; and 
 forming a conductive feature comprising a first portion extending into the recess to form an upper capacitor plate of the capacitor. 
 
     
     
       2. The method of  claim 1 , wherein the conductive feature further comprises:
 a second portion forming a floating gate of a transistor; and 
 a third portion connecting the first portion to the second portion, wherein the third portion is neither a part of the capacitor nor a part of the transistor. 
 
     
     
       3. The method of  claim 2  further comprising:
 forming a gate dielectric of the transistor over a second active region of the semiconductor substrate; and 
 when the conductive feature is formed, simultaneously forming the floating gate, with the floating gate electrically coupled to the upper capacitor plate. 
 
     
     
       4. The method of  claim 3 , wherein the forming the gate dielectric comprises, when the oxidizing the outer portion of the side surface layer is performed, simultaneously oxidizing a top surface portion of the second active region to form the gate dielectric. 
     
     
       5. The method of  claim 3 , wherein the forming the floating gate comprises forming a polysilicon region continuously extending over the first active region and the second active region. 
     
     
       6. A method comprising:
 forming a coupling capacitor comprising:
 etching a Shallow Trench Isolation (STI) region to form a recess, with a sidewall of a first active region of a semiconductor substrate exposed to the recess; 
 performing a first implantation to dope a sidewall surface portion of the first active region to form a first portion of a lower capacitor plate of the coupling capacitor, wherein the sidewall of the first active region is a sidewall of the sidewall surface portion; 
 oxidizing an outer portion of the sidewall surface portion to form an oxide layer, wherein an inner portion of the sidewall surface portion remains un-oxidized; and 
 forming a first conductive feature extending into the recess, wherein first the conductive feature comprises a sidewall contacting a sidewall of the oxide layer, with the first conductive feature configured as an upper capacitor plate of the coupling capacitor. 
 
 
     
     
       7. The method of  claim 6  further comprising forming a transistor comprising:
 forming a gate dielectric over a second active region of the semiconductor substrate; 
 forming a second conductive feature over the gate dielectric, wherein the first conductive feature and the second conductive feature are interconnected to form a floating gate; and 
 forming source and drain regions on opposite sides of the gate dielectric and the floating gate. 
 
     
     
       8. The method of  claim 6 , wherein the sidewall surface portion of the first active region is lower than a bottom surface of a top surface portion of the first active region, and the method further comprises:
 implanting the top surface portion of the first active region during the first implantation to form a second portion of the lower capacitor plate of the coupling capacitor; and 
 oxidizing an upper portion of the top surface portion of the first active region during the oxidizing the upper portion of the sidewall surface portion. 
 
     
     
       9. The method of  claim 6  further comprising performing a second implantation to dope the first active region and to form a well region, wherein the well region extends below a bottom end of the sidewall surface portion of the first active region. 
     
     
       10. The method of  claim 9 , wherein an energy for the first implantation is lower than an energy for the second implantation. 
     
     
       11. The method of  claim 6 , wherein in the first implantation, a lower portion of the first active region overlapped by the recess is doped to form a portion of the lower capacitor plate. 
     
     
       12. The method of  claim 11 , wherein the lower portion of the first active region is overlapped by a portion of the STI region. 
     
     
       13. A method comprising:
 forming a coupling capacitor comprising:
 etching a portion of a Shallow Trench Isolation (STI) region on a side of a portion of a first active region to form a recess, wherein the first active region is a part of a semiconductor substrate; 
 performing a first implantation to dope a first surface portion and a second surface portion of the first active region to form a lower capacitor plate, wherein the first surface portion is overlapped by a portion of the STI region, and the second surface portion is higher than a bottom surface of the STI region; 
 oxidizing an upper portion of the second surface portion to form an oxide layer, wherein a lower portion of the second surface portion remains to be a semiconductor region; and 
 forming a first portion of a floating gate over the oxide layer, with the first portion of the floating gate configured as an upper capacitor plate of the coupling capacitor. 
 
 
     
     
       14. The method of  claim 13 , wherein in the first implantation, a sidewall surface portion of the first active region is also implanted to form a part of the lower capacitor plate, and wherein the sidewall surface portion connects the second surface portion to the first surface portion of the first active region. 
     
     
       15. The method of  claim 14 , wherein in the oxidizing the upper portion of the second surface portion, an outer portion of the sidewall surface portion of the first active region is oxidized. 
     
     
       16. The method of  claim 14 , wherein in the oxidizing the upper portion of the second surface portion, an inner portion of the sidewall surface portion of the first active region is not oxidized. 
     
     
       17. The method of  claim 13  further comprising performing a second implantation to dope the first active region and to form a well region, wherein the well region extends below a bottom surface of the first portion of the first active region. 
     
     
       18. The method of  claim 17  further comprising forming a transistor comprising:
 forming a gate dielectric over a second active region of the semiconductor substrate; and 
 forming a second portion of the floating gate over the gate dielectric. 
 
     
     
       19. The method of  claim 1 , wherein during the implanting, both the outer portion and an inner portion of the side surface layer are implanted, and after the oxidizing, the inner portion remains un-oxidized. 
     
     
       20. The method of  claim 6 , wherein the STI region further comprises a lower portion overlapped by the etched portion of the STI region.