Semiconductor device assembly with underfill containment cavity

Abstract

Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first semiconductor die having a base region formed from a substrate material, a recessed surface along the base region, a peripheral region formed from the substrate material and projecting from the base region, and a sidewall surface along the peripheral region and defining a cavity with the sidewall surface in the peripheral region. The semiconductor device assembly further includes a thermal transfer structure attached to the peripheral region of the first die adjacent the cavity, and an underfill material at least partially filling the cavity and including a fillet between the peripheral region and the stack of second semiconductor dies.

We claim: 
     
       1. A semiconductor device assembly, comprising:
 a first semiconductor die having a base region formed from a substrate material, a recessed surface along the base region, a peripheral region formed from the substrate material and projecting from the base region, and a sidewall surface along the peripheral region, and wherein the recessed surface and the sidewall surface define a cavity within the peripheral region; 
 a stack of second semiconductor dies at least partially in the cavity; 
 a thermal transfer structure attached to the peripheral region of the first semiconductor die; and 
 an underfill material at least partially filling the cavity and including a fillet between the peripheral region and the stack of second semiconductor dies. 
 
     
     
       2. The semiconductor device assembly of  claim 1  wherein:
 the sidewall surface faces inwardly toward the stack of second semiconductor dies; and 
 the sidewall surface includes a portion that is exposed. 
 
     
     
       3. The semiconductor device assembly of  claim 2  wherein the fillet includes a first portion between the sidewall surface and the stack of second semiconductor dies, and a second portion between the thermal transfer structure and the stack of second semiconductor dies. 
     
     
       4. The semiconductor device assembly of  claim 1  wherein:
 the sidewall surface faces inwardly toward the stack of second semiconductor dies; and 
 the thermal transfer structure includes an inner surface that is generally coplanar with the sidewall surface. 
 
     
     
       5. The semiconductor device assembly of  claim 1  wherein:
 the sidewall surface defines a first sidewall surface that faces the stack of second semiconductor dies and the first semiconductor die further includes a second sidewall surface that extends away from the first sidewall surface at a non-zero angle; and 
 the underfill material at least partially covers the first sidewall surface and the second sidewall surface. 
 
     
     
       6. The semiconductor device assembly of  claim 1  wherein:
 the thermal structure includes a first wall portion and a second wall portion that define a recess; and 
 at least one of the second semiconductor dies is positioned within the recess. 
 
     
     
       7. The semiconductor device assembly of  claim 1  wherein the first semiconductor die includes a plurality of through-silicon vias extending through the base portion, and the through-silicon vias are electrically coupled to the stack of second semiconductor dies. 
     
     
       8. The semiconductor device assembly of  claim 1  wherein the first semiconductor die includes an integrated circuit. 
     
     
       9. The semiconductor device assembly of  claim 8  wherein the integrated circuit is located at least partially in the peripheral region. 
     
     
       10. The semiconductor device assembly of  claim 8  wherein:
 the integrated circuit is a logic circuit; and 
 the second semiconductor dies are memory dies. 
 
     
     
       11. The semiconductor device assembly of  claim 1  wherein the cavity has a depth of at least 200 μm. 
     
     
       12. The semiconductor device assembly of  claim 11  wherein the second semiconductor dies each have a thickness in a range of about 50 to about 200 μm. 
     
     
       13. The semiconductor device assembly of  claim 1  wherein the cavity has a depth of at least 300 μm. 
     
     
       14. The semiconductor device assembly of  claim 1  wherein the stack of second semiconductor dies includes at least two semiconductor dies in the cavity. 
     
     
       15. A semiconductor device assembly, comprising:
 a logic die having a cavity; 
 a first memory die in the cavity; 
 a thermal transfer structure attached to the logic die; 
 a second memory die on the first memory; and 
 an underfill material between the first and second memory dies, and at least partially filling the cavity. 
 
     
     
       16. The semiconductor device assembly of  claim 15 , further comprising a plurality of through-silicon vias beneath the first memory die and extending through the logic die. 
     
     
       17. The semiconductor device assembly of  claim 15  wherein:
 the logic die includes a sidewall surface adjacent the thermal transfer structure and separated from the first memory die by a gap; and 
 the underfill material includes a fillet at least in the gap. 
 
     
     
       18. The semiconductor device assembly of  claim 15  wherein the thermal transfer structure is attached to the second memory die. 
     
     
       19. The semiconductor device assembly of  claim 15  wherein the thermal transfer structure does not contact the underfill material. 
     
     
       20. The semiconductor device assembly of  claim 15  wherein the logic die includes:
 a peripheral region adjacent the cavity and attached to the thermal transfer structure; and 
 an integrated circuit component located at least partially in the peripheral region. 
 
     
     
       21. The semiconductor device assembly of  claim 20  wherein the integrated circuit component includes a serial/deserializer circuit. 
     
     
       22. A method of forming a semiconductor device assembly, comprising
 forming a cavity in a semiconductor substrate; 
 attaching a stack of semiconductor dies to a recessed surface in the cavity; 
 depositing an underfill material between individual semiconductor dies of the stack of semiconductor dies; 
 accumulating excess underfill material between the stack of semiconductor dies and a peripheral region of the substrate adjacent the cavity; and 
 attaching a thermal transfer structure to the peripheral region. 
 
     
     
       23. The method of  claim 22  wherein depositing the underfill material includes injecting the underfill material between the individual semiconductor dies. 
     
     
       24. The method of  claim 22 , further comprising attaching the thermal transfer structure to the stack of semiconductor dies. 
     
     
       25. The method of  claim 22  wherein forming the cavity includes etching a hole into the substrate to a depth of at least 200 μm. 
     
     
       26. The method of  claim 25 , further comprising thinning the substrate to a thickness of 300 μm or less. 
     
     
       27. The method of  claim 22  wherein forming the cavity includes etching a hole into the substrate to a depth of at least 300 μm. 
     
     
       28. The method of  claim 22  wherein:
 forming the cavity includes etching a hole in the substrate to expose a plurality of through-silicon vias (TSVs) at a base of the cavity; and 
 attaching the stack of semiconductor dies includes bonding bond pads of a bottom-most one of the semiconductor dies in the stack to the TSVs. 
 
     
     
       29. The method of  claim 22  wherein the semiconductor substrate includes an integrated circuit. 
     
     
       30. The method of  claim 22  wherein attaching the thermal transfer structure includes positioning at least one of the semiconductor dies in a recess of the thermal transfer structure. 
     
     
       31. A method of forming a semiconductor device assembly, comprising:
 positioning a stack of memory dies at least partially in a cavity of a logic die; 
 at least partially filling the cavity with an underfill material; 
 positioning at least one of the memory dies in a recess of a thermal transfer structure; and 
 attaching the thermal transfer structure to a peripheral region of the logic die adjacent the cavity. 
 
     
     
       32. The method of  claim 31  wherein at least partially filling the cavity with the underfill material includes flowing excess underfill material into a gap between the stack of memory dies and the peripheral region. 
     
     
       33. The method of  claim 31 , further comprising electrically coupling the stack of memory dies to a plurality of through-silicon vias at a base of the cavity. 
     
     
       34. The method of  claim 31 , further comprising attaching the thermal transfer structure to the at least one of the memory dies. 
     
     
       35. The method of  claim 31  wherein the logic die includes an integrated circuit component located at least partially in the peripheral region. 
     
     
       36. The method of  claim 35  wherein the integrated circuit component includes a serial/deserializer circuit.