Normally-off power JFET and manufacturing method thereof

Abstract

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

What is claimed is: 
     
       1. A method of manufacturing a junction field effect transistor, comprising the steps of:
 (a) providing on a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a first silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; 
 (b) forming a first structure having a plurality of first gate impurity regions by doping a surface of the first silicon-carbide-based semiconductor epitaxial layer with an impurity having a second conductivity type by ion implantation to introduce, into the surface of the first epitaxial layer, the plurality of first gate impurity regions; 
 (c) after the step (b), performing first activation annealing on the first structure; 
 (d) after the step (c), forming, on the surface of the first epitaxial layer , a second silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; 
 (e) forming a second structure having a plurality of second gate impurity regions by doping a surface of the second silicon-carbide-based semiconductor epitaxial layer with an impurity having the second conductivity type by ion implantation to introduce, into the surface of the second epitaxial layer, the plurality of second gate impurity regions respectively coupled to the plurality of first gate impurity regions; 
 (f) after the step (e), performing second activation annealing on the second structure; 
 (g) after the step (f), forming, over the second epitaxial layer, a third silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate; 
 (h) forming a third structure having a plurality of third gate impurity regions by doping a surface of the third silicon-carbide-based semiconductor epitaxial layer with an impurity having the second conductivity type by ion implantation to introduce, into the surface of the third epitaxial layer, the plurality of third gate impurity regions respectively coupled to the plurality of second gate impurity regions; 
 (i) after the step (h), performing third activation annealing on the third structure; and 
 (j) after the step (i), forming a source region of the first conductivity type between adjacent third gate impurity regions in the third epitaxial layer, 
 wherein a spacing between the third gate impurity regions is larger than a spacing between the second gate impurity regions. 
 
     
     
       2. A method of manufacturing a junction field effect transistor according to  claim 1 ,
 wherein the first activation annealing and the second activation annealing are each performed in a state where the first main surface of the semiconductor substrate is covered with a carbon-based film. 
 
     
     
       3. A method of manufacturing a junction field effect transistor according to  claim 2 ,
 wherein the third activation annealing is performed in a state where the first main surface of the semiconductor substrate is covered with a carbon-based film. 
 
     
     
       4. A method of manufacturing a junction field effect transistor according to  claim 1 ,
 wherein the plurality of third gate impurity regions are respectively coupled directly to the plurality of second gate impurity regions. 
 
     
     
       5. A method of manufacturing a junction field effect transistor according to  claim 1 ,
 wherein the plurality of third gate impurity regions are respectively coupled to the plurality of second gate impurity regions through intervening gate regions formed in a further silicon-carbide-based semiconductor epitaxial layer formed between the second and third epitaxial layers and having the first conductivity type and a lower impurity concentration than the semiconductor substrate. 
 
     
     
       6. A method of manufacturing a junction field effect transistor, comprising:
 successively forming, over a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a plurality of structures each including a respective silicon-carbide-based semiconductor epitaxial layer having the first conductivity type and a lower impurity concentration than the semiconductor substrate, and a respective plurality of gate impurity regions of a second conductivity type in the epitaxial layer, 
 the gate impurity regions of the plurality of structures being formed in correspondence with each other so as to be coupled from each structure to the next; 
 after forming each structure, subjecting the structure to activation annealing, with each structure other than an uppermost structure of the plurality of structures being subjected to the activation annealing prior to forming the next structure; and 
 forming a source region between adjacent gate impurity regions of the uppermost structure, 
 wherein the gate impurity regions of the uppermost structure are arranged with a greater spacing than a spacing between the gate impurity regions of a preceding structure. 
 
     
     
       7. A method of manufacturing a junction field effect transistor according to  claim 6 , wherein the activation annealing of at least some of the plurality of structures is performed in a state where the first main surface of the semiconductor substrate is covered with a carbon-based film. 
     
     
       8. A method of manufacturing a junction field effect transistor according to  claim 6 , wherein the activation annealing of all of the plurality of structures is performed in a state where the first main surface of the semiconductor substrate is covered with a carbon-based film.