US9576819B2ActiveUtilityA1

Techniques for increased dopant activation in compound semiconductors

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Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASS INCPriority: Jun 17, 2014Filed: Jun 17, 2015Granted: Feb 21, 2017
Est. expiryJun 17, 2034(~7.9 yrs left)· nominal 20-yr term from priority
H10P 30/206H10P 30/21H10P 95/904H01L 21/26546H01L 21/3245H10P 30/28
35
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15
Claims

Abstract

A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of doping a compound semiconductor substrate, wherein the compound semiconductor is In x Ga 1-x  As, comprising:
 setting a first substrate temperature for the compound semiconductor substrate in a first temperature range, wherein the first temperature range is between 50° C. and 100° C.; 
 implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and 
 annealing the compound semiconductor substrate after the implanting the ions, wherein, in conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range. 
 
     
     
       2. The method of  claim 1 , wherein the dopant species is silicon. 
     
     
       3. The method of  claim 1 , wherein x is equal to 0.53. 
     
     
       4. The method of  claim 1 , wherein the ion energy is from 200 eV to 30 keV and the dopant species is silicon. 
     
     
       5. The method of  claim 1 , wherein the first ion dose is from 1E14/cm 2  to 5E15/cm 2 . 
     
     
       6. The method of  claim 1 , wherein the implanting the dopant species comprises implanting ions of the dopant at an ion energy and ion dose to generate dechanneling of ions during the implanting of the dopant species at the first substrate temperature while not amorphizing the compound semiconductor. 
     
     
       7. The method of  claim 1 , wherein the annealing the compound semiconductor comprises performing annealing at a temperature in the range of 400° C. to 1000° C. for a duration of 1 ns to 60 sec. 
     
     
       8. A method of controlling implant damage in a compound semiconductor substrate, comprising:
 implanting a first ion dose of a dopant species at a first substrate temperature, wherein the first temperature is between 50° C. and 100° C., wherein the first ion dose and first substrate temperature are interoperative to induce dechanneling of the dopant species during implantation while not amorphizing a crystalline lattice of the compound semiconductor substrate; and 
 after the implanting, annealing the compound semiconductor substrate at an annealing temperature and annealing duration effective to activate the dopant species, wherein the compound semiconductor is In x Ga 1-x , and wherein x is equal to 0.53. 
 
     
     
       9. The method of  claim 8 , wherein, in conjunction with the annealing, the first ion dose is effective to generate a first dopant activation at the first substrate temperature higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first substrate temperature, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first substrate temperature. 
     
     
       10. The method of  claim 8 , wherein the dopant species is silicon. 
     
     
       11. The method of  claim 8 , wherein the annealing the compound semiconductor comprises performing annealing at a temperature ranging from 400° C. to 1000° C. for a duration of 1 ns to 60 sec. 
     
     
       12. A method of increasing dopant activation in a In x Ga 1-x  As substrate, comprising:
 setting a first substrate temperature for the In x Ga 1-x  As substrate in a first temperature range; 
 implanting silicon into the compound In x Ga 1-x  As substrate at a first ion dose at the first substrate temperature; and 
 annealing the In x Ga 1-x  As substrate substrate after the implanting the ions, wherein, in conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range, wherein the first temperature range is between 50° C. and 140° C. 
 
     
     
       13. The method of  claim 12 , wherein x=0.53, and the first substrate temperature is between 50° C. and 100° C. 
     
     
       14. The method of  claim 13 , wherein the annealing comprises annealing the In x Ga 1-x  As substrate at a temperature of 750° C. for five seconds. 
     
     
       15. The method of  claim 14 , wherein the first ion dose is from 1E14/cm 2  to 5E15/cm 2 .

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