FinFET isolation structure and method for fabricating the same

Abstract

A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a semiconductor substrate; 
 a stop layer on the semiconductor substrate; 
 a semiconductor fin on the stop layer; and 
 two cells adjacent to each other on the semiconductor fin, the semiconductor fin having a fin isolation structure at a common boundary that is shared by the two cells, the fin isolation structure having an air gap extending from a top of the semiconductor fin to the stop layer, wherein the air gap divides the semiconductor fin into two portions of the semiconductor fin, the fin isolation structure comprising a dielectric cap layer capping a top of the air gap. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the two portions of the semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm. 
     
     
       3. The semiconductor device of  claim 1 , wherein the dielectric cap layer comprises silicon oxide or silicon nitride. 
     
     
       4. The semiconductor device of  claim 1 , wherein the stop layer comprises SiGeO x , SiGe, SiO x , SiP or SiPO x , where x is greater than 0. 
     
     
       5. The semiconductor device of  claim 1 , wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm. 
     
     
       6. The semiconductor device of  claim 1 , wherein the air gap has a first air gap on the stop layer, and a second air gap above the first air gap, and a width of a bottom of the first air gap is greater than a width of a bottom of the second air gap. 
     
     
       7. The semiconductor device of  claim 1 , where the air gap extends from a top of the semiconductor fin to a portion of the semiconductor substrate through the stop layer. 
     
     
       8. The semiconductor device of  claim 5 , wherein the air gap has a flat bottom enclosed by an arc surface, and a width of the flat bottom of the air gap is smaller than a width of a top of the dielectric cap layer. 
     
     
       9. The semiconductor device of  claim 1 , wherein the fin isolation structure further comprises:
 two dummy gate spacers respectively on the two portions of the semiconductor fin and sandwiching the dielectric cap layer. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein the air gap extends between a portion of the dummy gate spacers. 
     
     
       11. A semiconductor device, comprising:
 a semiconductor substrate; 
 a stop layer on the semiconductor substrate; and 
 a semiconductor fin on the stop layer, each of two opposite ends of the semiconductor fin having a fin isolation structure, the fin isolation structure having an air gap extending from a top of the semiconductor fin to the stop layer, wherein the air gap divides the semiconductor fin into two portions of the semiconductor fin, the fin isolation structure comprising a dielectric cap layer capping a top of the air gap. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the two portions of the semiconductor fin are spaced at a distance substantially in a range from 5 nm to 50 nm. 
     
     
       13. The semiconductor device of  claim 11 , wherein the stop layer has a thickness substantially in a range from 1 nm to 50 nm. 
     
     
       14. The semiconductor device of  claim 11 , wherein the air gap has a first air gap on the stop layer, and a second air gap above the first air gap, and a width of a bottom of the first air gap is greater than a width of a bottom of the second air gap. 
     
     
       15. The semiconductor device of  claim 11 , wherein the air gap extends from a top of the semiconductor fin to a portion of the semiconductor substrate through the stop layer. 
     
     
       16. The semiconductor device of  claim 15 , wherein the air gap has a flat bottom enclosed by an arc surface, and a width of the flat bottom of the air gap is smaller than a width of a top of the air gap. 
     
     
       17. A method for forming a semiconductor device, the method comprising:
 forming a stop layer on a semiconductor substrate; 
 forming a semiconductor fin on the stop layer; 
 forming two cells adjacent to each other on the semiconductor fin; 
 forming a gate conductor on a top of the semiconductor fin at a common boundary that is shared by the two cells; 
 forming a gate spacer peripherally enclosing the gate conductor; 
 etching the gate conductor and the semiconductor fin to form a air gap extending from a top of the semiconductor fin to the stop layer, thereby dividing the semiconductor fin into two portions of the semiconductor fin; and 
 depositing a dielectric cap layer into the air gap to cap a top of the air gap. 
 
     
     
       18. The method of  claim 17 , wherein the operation of etching the gate conductor and the semiconductor fin further etches the stop layer and a portion of semiconductor. 
     
     
       19. The method of  claim 18 , wherein the operation of etching etches the stop layer by using C x F y , NF x , N 2 , O 2 , Cl 2 , Ar, SF x , C x H y F z  or HBr as an etchant, where x and y are greater than 0. 
     
     
       20. The method of  claim 17 , wherein the operation of forming the stop layer is performed by implantation or atomic layer deposition (ALD).