Isolation structure

Abstract

A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.

What is claimed is: 
     
       1. A structure comprising:
 a p-type substrate; 
 a deep n-type well adjacent to the p-type substrate and having a first conductive path to a first terminal; 
 a deep p-type well
 in the deep n-type well, 
 the deep p-type well is separated from the p-type substrate by the deep n-type well, and 
 the deep p-type well has a second conductive path to a second terminal, the second terminal being configured to bias the deep p-type well; 
 
 a first n-type well over the deep p-type well; 
 a first p-type well over the deep p-type well, wherein the deep p-type well has a third conductive path through the first p-type well to a third terminal; 
 a gate structure of a transistor over and partially overlapping the first n-type well and the first p-type well; 
 a first n+ type doped region in the first n-type well; 
 a drain terminal of the transistor over and in contact with the first n+ type doped region; 
 a source terminal of the transistor over the first p-type well, 
 wherein the deep n-type well comprises a thickness thicker than a thickness of the deep p-type well, 
 the thickness of the deep p-type well is selected based on a voltage applied to the deep p-type well from the third terminal through the third conductive path, 
 a ratio of the thickness of the deep p-type well to the thickness of the deep n-type well is 2:3, and 
 the thickness of the deep n-type well is selected based on a voltage punch-through. 
 
     
     
       2. The structure of  claim 1 , wherein
 a portion of the deep p-type well is not adjacent to the first n-type well. 
 
     
     
       3. The structure of  claim 1 , wherein
 the first conductive path includes
 a second n-type well; 
 a second n+ type doped region in the second n-type well; and 
 the first terminal over and in contact with the second n+ type doped region; and 
 
 the first terminal is configured to bias the deep n-type well. 
 
     
     
       4. A structure comprises:
 a p-type substrate; 
 a deep n-well over the p-type substrate; 
 a deep p-well separated from the p-type substrate by the deep n type n well; 
 a first n-type well over and in contact with the deep p-well; 
 a first p-type well over and in contact with the deep p-well; 
 a second p-type well over and in contact with the deep p-well and the deep n-well; 
 a second n-type well over and in contact with the deep n-well; 
 a gate structure of a transistor over and partially overlapping the first n-type well and the first p-type well; 
 a first n+ type doped region in the first n-type well; 
 a first terminal configured to bias the deep p-type well through the second p-type well; 
 a second terminal configured to bias the deep p-type well through the first p-type well; 
 a drain terminal of the transistor over and in contact with the first n+ type doped region; and 
 a source terminal of the transistor over the first p-type well, 
 wherein a ratio of a thickness of the deep p-well to a thickness of the deep n-well is 2:3, and 
 the thickness of the deep p-well and the thickness of the deep n-well are selected based on a voltage punch-through. 
 
     
     
       5. The structure of  claim 4 , further comprising:
 a conductive path through the second n-type well to the deep n-well. 
 
     
     
       6. The structure of  claim 4 , further comprising:
 a second n+ type doped region in the second n-type well; and 
 a third terminal over and in contact with the second n+ type doped region, 
 wherein
 the second n+ type doped region and the third terminal are electrically connected with the second n-type well and with the deep n-well. 
 
 
     
     
       7. The structure of  claim 4 , wherein
 the first p-type well is over and in contact with the deep n-well. 
 
     
     
       8. The structure of  claim 4 , wherein
 a portion of the deep p-well is under the first p-type well, and is determined based on conductive connection between the deep p-well and the first p-type well. 
 
     
     
       9. A method comprising:
 forming a deep n-type well adjacent to a p-type substrate; 
 forming a deep p-type well in the deep n-type well, the deep p-type well separated from the p-type substrate by the deep n-type well; 
 forming a first n-type well over the deep p-type well; 
 forming a first p-type well over the deep p-type well, wherein the first p-type well serves as a first conductive path from the deep p-type well to a first terminal, the first terminal being configured to bias the deep p-type well, and a portion of the deep p-type well in electrical connection with the first p-type well is determined based on conductive connection between the deep p-type well and the first p-type well; 
 forming a gate structure of a transistor over and partially overlapping the first n-type well and the first p-type well; 
 forming a first n+ type doped region in the first n-type well; 
 forming a p+ type doped region or a p-type lightly doped drain (LDD) region in the first n-type well; 
 forming a drain terminal of the transistor over and in contact with the first n+ type doped region; 
 forming a source terminal of the transistor over the first p-type well; 
 forming a second conductive path configured to bias the deep p-type well; 
 wherein a thickness of the deep n-type well is different than a thickness of the deep p-type well, 
 the thickness of the deep p-type well is selected based on a voltage applied to the deep p-type well from the first terminal through the first conductive path, 
 the thickness of the deep p-type well and the thickness of the deep n-type well are selected based on a voltage punch-through, and 
 a ratio of the thickness of the deep p-type well to the thickness of the deep n-type well is 2:3. 
 
     
     
       10. The method of  claim 9 , wherein
 the deep p-type well is formed by ion implantation of boron or of boron diflouride. 
 
     
     
       11. The method of  claim 9 , wherein
 the deep p-type well is formed by ion implantation of boron or of boron diflouride with a voltage in the kiloelectron volts. 
 
     
     
       12. The method of  claim 9 , wherein
 the thickness of the deep n-type well is greater than the thickness of the deep p-type well. 
 
     
     
       13. The structure of  claim 1 , further comprising a second n+ type doped region in the first p-type well, the source terminal of the transistor being over and in contact with the second n+ type doped region. 
     
     
       14. The structure of  claim 4 , further comprising a second n+ type doped region in the first p-type well, the source terminal of the transistor being over and in contact with the second n+ type doped region. 
     
     
       15. The structure of  claim 1 , wherein
 the deep n-type well is in contact with a second n-type well and a second p-type well. 
 
     
     
       16. The structure of  claim 1 , wherein
 the second conductive path includes
 a second p-type well; 
 a p-type doped region in the second p-type well; and 
 the second terminal. 
 
 
     
     
       17. The structure of  claim 4 , comprising
 a p-type region, 
 wherein
 the p-type region and the first terminal are electrically connected with the second p-type well and with the deep p-well. 
 
 
     
     
       18. The method of  claim 9 , further comprising:
 forming a second p-type well over the deep p-well; and 
 forming a second terminal over the second p-type well, wherein the second p-type well serves as the second conductive path from the deep p-type well to the second terminal. 
 
     
     
       19. The structure of  claim 1 , wherein
 a combined thickness of the thickness of the deep n-type well and the thickness of the deep p-type well is between 200 nm and 1,500 nm. 
 
     
     
       20. The structure of  claim 4 , wherein
 a combined thickness of the thickness of the deep n-well and the thickness of the deep p-well is between 200 nm and 1,500 nm. 
 
     
     
       21. The structure of  claim 9 , wherein
 a combined thickness of the thickness of the deep n-type well and the thickness of the deep p-type well is between 200 nm and 1,500 nm.