Vertical single electron transistor formed by condensation

Abstract

A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer.

What is claimed is: 
     
       1. A method for forming a vertical single electron transistor, comprising;
 forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire; 
 depositing an oxide to cover the SiGe region; 
 performing a condensation process to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire; 
 forming a bottom contact about the lower portion; 
 forming a first dielectric layer on the bottom contact; 
 forming a gate structure about the island on the first dielectric layer; 
 forming a second dielectric layer on the gate structure; and 
 forming a top contact on the second dielectric layer. 
 
     
     
       2. The method as recited in  claim 1 , wherein the island includes a quantum dot having a diameter of less than about 6 nm. 
     
     
       3. The method as recited in  claim 1 , wherein the upper portion and lower portion include doped Si. 
     
     
       4. The method as recited in  claim 1 , wherein at least one of the first dielectric layer and/or the second dielectric layer are formed using a directional deposition method. 
     
     
       5. The method as recited in  claim 4 , wherein the directional deposition method includes a gas cluster ion beam (GCIB) method. 
     
     
       6. The method as recited in  claim 1 , wherein forming the heterostructured nanowire includes:
 lithographically etching a stack of layers to form one or more fins; and 
 lithographically etching the one or more fins in a fin cut etch to form one or more nanowires. 
 
     
     
       7. The method as recited in  claim 1 , wherein forming the heterostructured nanowire includes:
 patterning metal seeds on a semiconductor layer; and 
 growing nanowires by a vapor liquid solid growth method. 
 
     
     
       8. The method as recited in  claim 1 , further comprising trimming an area around the island to form a necked down region about the island. 
     
     
       9. A method for forming a vertical single electron transistor, comprising;
 forming a nanowire from a first doped silicon layer, a SiGe layer, and a second doped silicon layer on a semiconductor substrate; 
 depositing an oxide to cover the nanowire; 
 performing a condensation process to convert the SiGe to oxide and condense Ge to form an island between the first doped silicon layer and the second doped silicon layer of the nanowire; 
 forming a source region about the first doped silicon layer; 
 forming a gate structure about the island between the first doped silicon layer and the second doped silicon layer of the nanowire; and 
 forming a drain region about the second doped silicon layer. 
 
     
     
       10. The method as recited in  claim 9 , wherein the island includes a quantum dot having a diameter of less than about 6 nm. 
     
     
       11. The method as recited in  claim 9 , wherein the drain region is separated from the gate structure by a first dielectric layer and the source region is separated from the gate structure by a second dielectric layer. 
     
     
       12. The method as recited in  claim 11 , wherein the first and second dielectric layers are formed by a directional deposition method including a gas cluster ion beam (GCIB) method. 
     
     
       13. The method as recited in  claim 9 , wherein forming the nanowire includes:
 lithographically etching the first doped silicon layer, the SiGe layer, and the second doped silicon layer on the semiconductor substrate to form one or more fins; and 
 lithographically etching the one or more fins in a fin cut etch to form one or more nanowires. 
 
     
     
       14. The method as recited in  claim 9 , wherein forming the nanowire includes:
 patterning metal seeds on a doped silicon layer; and 
 growing nanowires by a vapor liquid solid growth method to form the first doped silicon layer, the SiGe layer, and the second doped silicon layer. 
 
     
     
       15. The method as recited in  claim 9 , further comprising trimming an area around the island to form a necked down region about the island. 
     
     
       16. A vertical single electron transistor, comprising;
 a nanowire having a lower doped layer and an upper doped layer; 
 a dielectric gap disposed between the lower doped layer and the upper doped layer; 
 a quantum dot formed within the dielectric gap and encapsulated in dielectric material; 
 a source region formed about one of the lower doped layer and the upper doped layer; 
 a gate structure formed about the quantum dot; and 
 a drain region formed about the other of the lower doped layer and the upper doped layer. 
 
     
     
       17. The transistor as recited in  claim 16 , wherein the quantum dot includes a diameter of less than about 6 nm. 
     
     
       18. The transistor as recited in  claim 16 , wherein drain region is separated from the gate structure by a first dielectric layer and the source is separated from the gate structure by a second dielectric layer. 
     
     
       19. The transistor as recited in  claim 16 , further comprising a necked down region in an area around the quantum dot. 
     
     
       20. The transistor as recited in  claim 16 , wherein the quantum dot includes condensed Ge.