One-time programmable memory array having small chip area

Abstract

A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

What is claimed is: 
     
       1. A memory cell comprising:
 a first select transistor having a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line; 
 a first following gate transistor having a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line; 
 an antifuse transistor having a first terminal coupled to the second terminal of the first following gate transistor, a second terminal, and a gate terminal coupled to an antifuse control line; 
 a second following gate transistor having a first terminal coupled to the second terminal of the antifuse transistor, a second terminal, and a gate terminal coupled to the following control line; and 
 a second select transistor having a first terminal coupled to the second terminal of the second following gate transistor, a second terminal coupled to the bit line, and a gate terminal coupled to the word line. 
 
     
     
       2. The memory cell of  claim 1 , wherein:
 the first select transistor further comprises a first source/drain extension region coupled to the first terminal of the first select transistor and a second source/drain extension region coupled to the second terminal of the first select transistor, the first source/drain extension region and the second source/drain extension region of the first select transistor are disposed below the gate terminal of the first select transistor; 
 the first following gate transistor further comprises a first source/drain extension region coupled to the first terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the second following gate transistor comprises a first source/drain extension region coupled to the second terminal of the second following gate transistor and below the gate terminal of the second following gate transistor; and 
 the second select transistor comprises a first source/drain extension region coupled to the first terminal of the second select transistor and a second source/drain extension region coupled to the second terminal of the second select transistor, the first source/drain extension region and the second source/drain extension region of the second select transistor are disposed below the gate terminal of the second select transistor. 
 
     
     
       3. The memory cell of  claim 2 , wherein the antifuse transistor is a metal-oxide-semiconductor capacitor. 
     
     
       4. The memory cell of  claim 2 , wherein:
 the first following gate transistor further comprises a second source/drain extension region coupled to the second terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the antifuse transistor further comprises a first source/drain extension region coupled to the first terminal of the antifuse transistor and a second source/drain extension region coupled to the second terminal of the antifuse transistor, the first source/drain extension region and the second source/drain extension region of the antifuse transistor are disposed below the gate terminal of the antifuse transistor; and 
 the second following gate transistor comprises a second source/drain extension region coupled to the first terminal of the second following gate transistor and below the gate terminal of the second following gate transistor. 
 
     
     
       5. The memory cell of  claim 4 , wherein the antifuse transistor is a metal-oxide-semiconductor capacitor. 
     
     
       6. The memory cell of  claim 2 , wherein:
 the first following gate transistor further comprises a modified source/drain extension region coupled to the second terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the antifuse transistor further comprises a modified source/drain extension region coupled to the first terminal and the second terminal of the antifuse transistor and below the gate terminal of the antifuse transistor; and 
 the second following gate transistor comprises a modified source/drain extension region coupled to the first terminal of the second following gate transistor and below the gate terminal of the second following gate transistor. 
 
     
     
       7. The memory cell of  claim 6 , wherein the antifuse transistor is an antifuse varactor. 
     
     
       8. The memory cell of  claim 2 , wherein:
 the second terminal of the first following gate transistor, the first terminal and the second terminal of the antifuse transistor, and the first terminal of the second following gate transistor are disposed in a well. 
 
     
     
       9. The memory cell of  claim 8 , wherein:
 the first select transistor, the first following gate transistor, the second select transistor, and the second following gate transistor are formed by N-type metal-oxide-semiconductor field effect transistors; and 
 the well is an N-well. 
 
     
     
       10. The memory cell of  claim 8 , wherein the antifuse transistor is an antifuse varactor. 
     
     
       11. The memory cell of  claim 1 , wherein a gate oxide thickness of the gate terminal of first select transistor, a gate oxide thickness of the gate terminal of first following gate transistor, a gate oxide thickness of the gate terminal of antifuse transistor, a gate oxide thickness of the gate terminal of second following gate transistor, and a gate oxide thickness of the gate terminal of second select transistor are substantially the same. 
     
     
       12. The memory cell of  claim 1 , wherein a gate oxide thickness of the gate terminal of first select transistor, a gate oxide thickness of the gate terminal of first following gate transistor, a gate oxide thickness of the gate terminal of second following gate transistor, and a gate oxide thickness of the gate terminal of second select transistor are substantially the same and are greater than a gate oxide thickness of the gate terminal of the antifuse transistor. 
     
     
       13. A memory array comprising a plurality of memory cells, each comprising:
 a first select transistor having a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line; 
 a first following gate transistor having a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line; 
 an antifuse transistor having a first terminal coupled to the second terminal of the first following gate transistor, a second terminal, and a gate terminal coupled to an antifuse control line; 
 a second following gate transistor having a first terminal coupled to the second terminal of the antifuse transistor, a second terminal, and a gate terminal coupled to the following control line; and 
 a second select transistor having a first terminal coupled to the second terminal of the second following gate transistor, a second terminal coupled to the bit line, and a gate terminal coupled to the word line; 
 wherein: 
 memory cells disposed in a same column are disposed in a same active area. 
 
     
     
       14. The memory cell of  claim 13 , wherein:
 the first select transistor further comprises a first source/drain extension region coupled to the first terminal of the first select transistor and a second source/drain extension region coupled to the second terminal of the first select transistor, the first source/drain extension region and the second source/drain extension region of the first select transistor are disposed below the gate terminal of the first select transistor; 
 the first following gate transistor further comprises a first source/drain extension region coupled to the first terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the second following gate transistor comprises a first source/drain extension region coupled to the second terminal of the second following gate transistor and below the gate terminal of the second following gate transistor; and 
 the second select transistor comprises a first source/drain extension region coupled to the first terminal of the second select transistor and a second source/drain extension region coupled to the second terminal of the second select transistor, the first source/drain extension region and the second source/drain extension region of the second select transistor are disposed below the gate terminal of the second select transistor. 
 
     
     
       15. The memory array of  claim 14 , wherein the antifuse transistor is a metal-oxide-semiconductor capacitor. 
     
     
       16. The memory cell of  claim 14 , wherein:
 the first following gate transistor further comprises a second source/drain extension region coupled to the second terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the antifuse transistor further comprises a first source/drain extension region coupled to the first terminal of the antifuse transistor and a second source/drain extension region coupled to the second terminal of the antifuse transistor, the first source/drain extension region and the second source/drain extension region of the antifuse transistor are disposed below the gate terminal of the antifuse transistor; and 
 the second following gate transistor comprises a second source/drain extension region coupled to the first terminal of the second following gate transistor and below the gate terminal of the second following gate transistor. 
 
     
     
       17. The memory array of  claim 16 , wherein the antifuse transistor is a metal-oxide-semiconductor capacitor. 
     
     
       18. The memory array of  claim 14 , wherein:
 the first following gate transistor further comprises a modified source/drain extension region coupled to the second terminal of the first following gate transistor and below the gate terminal of the first following gate transistor; 
 the antifuse transistor further comprises a modified source/drain extension region coupled to the first terminal and the second terminal of the antifuse transistor and below the gate terminal of the antifuse transistor; and 
 the second following gate transistor comprises a modified source/drain extension region coupled to the first terminal of the second following gate transistor and below the gate terminal of the second following gate transistor. 
 
     
     
       19. The memory array of  claim 18 , wherein the antifuse transistor is an antifuse varactor. 
     
     
       20. The memory array of  claim 14 , wherein:
 the second terminal of the first following gate transistor, the first terminal and the second terminal of the antifuse transistor, and the first terminal of the second following gate transistor are disposed in a well. 
 
     
     
       21. The memory array of  claim 20 , wherein:
 the first select transistor, the first following gate transistor, the second select transistor, and the second following gate transistor are formed by N-type metal-oxide-semiconductor field effect transistors; and 
 the well is an N-well. 
 
     
     
       22. The memory array of  claim 21 , wherein the antifuse transistor is an antifuse varactor. 
     
     
       23. The memory array of  claim 13 , wherein a gate oxide thickness of the gate terminal of first select transistor, a gate oxide thickness of the gate terminal of first following gate transistor, a gate oxide thickness of the gate terminal of antifuse transistor, a gate oxide thickness of the gate terminal of second following gate transistor, and a gate oxide thickness of the gate terminal of second select transistor are substantially the same. 
     
     
       24. The memory array of  claim 13 , wherein a gate oxide thickness of the gate terminal of first select transistor, a gate oxide thickness of the gate terminal of first following gate transistor, a gate oxide thickness of the gate terminal of second following gate transistor, and a gate oxide thickness of the gate terminal of second select transistor are substantially the same and are greater than a gate oxide thickness of the gate terminal of antifuse transistor. 
     
     
       25. The memory array of  claim 13 , wherein:
 memory cells disposed in a same row are coupled to a same antifuse control line, a same following control line, a same word line, and different bit lines; and 
 memory cells disposed in a same column are coupled to different antifuse control lines, different word lines, the same following control line, and a same bit line. 
 
     
     
       26. The memory array of  claim 25 , wherein:
 during a program operation of the memory cell:
 the word line is in a range from a first voltage to a second voltage; 
 the following control line in a range from the second voltage to a third voltage; 
 the antifuse control line is at the third voltage; and 
 the bit line is at a fourth voltage; and 
 
 the third voltage is greater than the second voltage, the second voltage is greater than the first voltage, and the first voltage is greater than the fourth voltage. 
 
     
     
       27. The memory array of  claim 26 , wherein:
 during the program operation of the memory cell:
 a bit line coupled to an unselected memory cell disposed in a same row as the memory cell is at the first voltage. 
 
 
     
     
       28. The memory array of  claim 26 , wherein:
 during the program operation of the memory cell:
 a word line coupled to an unselected memory cell disposed in a same column as the memory cell is at the fourth voltage; and 
 an antifuse control line coupled to the unselected memory cell is at the fourth voltage. 
 
 
     
     
       29. The memory array of  claim 25 , wherein:
 during a read operation of the memory cell:
 the word line is at a first voltage; 
 the following control line is at the first voltage; 
 the antifuse control line is in a range from the first voltage to a second voltage; and 
 the bit line is at a fourth voltage; and 
 
 the second voltage is greater than the first voltage, and the first voltage is greater than the fourth voltage. 
 
     
     
       30. The memory array of  claim 29 , wherein:
 during the read operation of the memory cell:
 a bit line coupled to an unselected memory cell disposed in a same row as the memory cell is at the first voltage. 
 
 
     
     
       31. The memory array of  claim 29 , wherein:
 during the read operation of the memory cell:
 a word line coupled to an unselected memory cell disposed in a same column as the memory cell is at the fourth voltage; and 
 an antifuse control line coupled to the unselected memory cell is at the fourth voltage. 
 
 
     
     
       32. The memory array of  claim 25 , wherein:
 during a reverse read operation of the memory cell:
 the word line is in a range from a first voltage to a second voltage; 
 the following control line in a range from the first voltage to the second voltage; 
 the antifuse control line is at a fourth voltage; and 
 the bit line is in a range from the first voltage to the second voltage; and 
 
 the second voltage is greater than the first voltage, and the first voltage is greater than the fourth voltage. 
 
     
     
       33. The memory array of  claim 32 , wherein:
 during the reverse read operation of the memory cell:
 a bit line coupled to an unselected memory cell disposed in a same row as the memory cell is at the fourth voltage. 
 
 
     
     
       34. The memory array of  claim 32 , wherein:
 during the reverse read operation of the memory cell:
 a word line coupled to an unselected memory cell disposed in a same column as the memory cell is at the fourth voltage; and 
 an antifuse control line coupled to the unselected memory cell is at the fourth voltage.